• Title/Summary/Keyword: DMR(Dual Modular Redundancy)

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Performance Analysis of Checkpointing and Dual Modular Redundancy for Fault Tolerance of Real-Time Control System (실시간 제어 시스템의 결함 극복을 위한 이중화 구조와 체크포인팅 기법의 성능 분석)

  • Ryu, Sang-Moon
    • Journal of Institute of Control, Robotics and Systems
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    • v.14 no.4
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    • pp.376-380
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    • 2008
  • This paper deals with a performance analysis of real-time control systems, which engages DMR(dual modular redundancy) to detect transient errors and checkpointing technique to tolerate transient errors. Transient errors are caused by transient faults and the most significant type of errors in reliable computer systems. Transient faults are assumed to occur according to a Poisson process and to be detected by a dual modular redundant structure. In addition, an equidistant checkpointing strategy is considered. The probability of the successful task completion in a real-time control system where periodic checkpointing operations are performed during the execution of a real-time control task is derived. Numerical examples show how checkpoiniting scheme influences the probability of task completion. In addition, the result of the analysis is compared with the simulation result.

A New Hardening Technique Against Radiation Faults in Asynchronous Digital Circuits Using Double Modular Redundancy (이중화 구조를 이용한 비동기 디지털 시스템의 방사선 고장 극복)

  • Kwak, Seong Woo;Yang, Jung-Min
    • Journal of Institute of Control, Robotics and Systems
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    • v.20 no.6
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    • pp.625-630
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    • 2014
  • Asynchronous digital circuits working in military and space environments are often subject to the adverse effects of radiation faults. In this paper, we propose a new hardening technique against radiation faults. The considered digital system has the structure of DMR (Double Modular Redundancy), in which two sub-systems conduct the same work simultaneously. Based on the output feedback, the proposed scheme diagnoses occurrences of radiation faults and realizes immediate recovery to the normal behavior by overriding parts of memory bits of the faulty sub-system. As a case study, the proposed control scheme is applied to an asynchronous dual ring counter implemented in VHDL code.

Development of the High Reliable Safety PLC for the Nuclear Power Plants (고신뢰도 안전등급 제어기기 개발)

  • Son, Kwang-Seop;Kim, Dong-Hoon;Son, Choul-Woong
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.62 no.1
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    • pp.109-119
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    • 2013
  • This paper presents the design of the Safety Programmable Logic Controller (SPLC) used in the Nuclear Power Plants, an analysis of a reliability for the SPLC using a markov model. The architecture of the SPLC is designed to have the multiple modular redundancy composed of the Dual Modular Redundancy(DMR) and the Triple Modular Redundancy(TMR). The operating system of the SPLC is designed to have the non-preemptive state based scheduler and the supervisory task managing the sequential scheduling, timing of tasks, diagnostic and security. The data communication of the SPLC is designed to have the deterministic state based protocol, and is designed to satisfy the effective transmission capacity of 20Mbps. Using Markov model, the reliability of SPLC is analyzed, and assessed. To have the reasonable reliability such as the mean time to failure (MTTF) more than 10,000 hours, the failure rate of each SPLC module should be less than $2{\times}10^{-5}$/hour. When the fault coverage factor (FCF) is increased by 0.1, the MTTF is improved by about 4 months, thus to enhance the MTTF effectively, it is needed that the diagnostic ability of each SPLC module should be strengthened. Also as the result of comparison the SPLC and the existing safety grade PLCs, the reliability and MTTF of SPLC is up to 1.6-times and up to 22,000 hours better than the existing PLCs.