• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.147-150
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• 2004

In this paper, we propose a reduced-state sequence estimation (RSSE) for trellis coded modulation (TCM) in OFDM with two-stage IDFT/ DFTs, MMSE-LE, and interleaving on frequency selective Rayleigh fading channels. The Viterbi algorithm (VA) is used to search for the best path through the reduced-state trellis combined with equalization and TCM decoding. Computer simulations confirm the bit error probability of the proposed scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.3A
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• pp.189-197
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• 2011

OFDM systems are much studied for the recent high speed wireless optical communication system. OFDM system has basically high PAPR and ICI easily generated because of non-linearity and RF impairments. In the wireless optical communication system, optical output power driven by current of LED is not linear so that transmission signals are distorted. Therefore, research about reception performance of this nonlinear optical output emitted by non-linear LED transfer function and OFDM signal has been conducted. Nonlinear effect of LED is different from nonlinear effect of OFDM system in the conventional radio communication system, which degrades the BER performance. In this paper, we apply non-linear transfer function of recently studied LED into OFDM system. So, for reducing the PAPR and suppressing the ICI in frequency domain of receiver, we suggest a new PAPR reduction technique to reduce non-linear distortion of LED and an adaptive ICI suppression algorithm so that BER performance may be improved. Also, the proposed method is verified through simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8B
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• pp.787-795
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• 2002

This paper presents the architecture and the implementation of a 2K/4K/8K-point complex Fast Fourier Transform(FFT) processor for Orthogonal Frequency-Division Multiplexing (OFDM) system. The architecture is based on the Cooley-Tukey algorithm for decomposing the long DFT into short length multi-dimensional DFTs. The transposition memory, shuffle memory, and memory mergence method are used for the efficient manipulation of data for multi-dimensional transforms. Booth algorithm and the COordinate Rotation DIgital Computer(CORDIC) processor are employed for the twiddle factor multiplications in each dimension. Also, for the CORDIC processor, a new twiddle factor generation method is proposed to obviate the ROM required for storing the twiddle factors. The overall 2K/4K/8K-FFT processor requires 600,000 gates, and it is implemented in 1.8 V, 0.18 ${\mu}m$ CMOS. The processor can perform 8K-point FFT in every 273 ${\mu}s$, 2K-point every 68.26 ${\mu}s$ at 30MHz, and the SNR is over 48dB, which are enough performances for the OFDM in DVB-T.