• Journal of the Korea Society for Simulation
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• v.27 no.3
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• pp.23-36
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• 2018

Discrete Event System Specification (DEVS) has been used for decades as it provides sound semantics for hierarchical modular specification of discrete event systems. Instead of the mathematical specification, the DEVS diagram, based on the structured DEVS formalism, has provided more intuitive and convenient representation of complex DEVS models. This paper proposes a clean room process for implementation and verification of a DEVS diagram model specification into a simulation software source code. Specifically, it underlies a sequence of transformation steps from conformance and integrity checking of a given diagram model, translation into a corresponding tabular model, and finally conversion to a simulation source code, with each step being inversely verifiable for traceability. A simple example helps developers to understand the proposed process with associated transformation methods; a case study shows that the proposed process is effective for and adaptable to practical simulation software development.

• Journal of the Korea Society for Simulation
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• v.21 no.2
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• pp.19-30
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• 2012

In recent decades, it has been known that the Discrete Event System Specification, or DEVS, formalism provides sound semantics to design a modular and hierarchical model of a discrete event system. In spite of this benefit, practitioners have difficulties in applying the semantics to real-world systems modeling because DEVS needs to specify a large size of sets of events and/or states in an unstructured form. To resolve the difficulties, this paper proposes an extension of the DEVS formalism, called the Structured DEVS formalism, with an associated graphical representation, called the DEVS diagram, by means of structural representation of such sets based on closure property of set theory. The proposed formalism is proved to be equivalent to the original DEVS formalism in their model specification, yet the new formalism specifies sets in a structured form with a concept of phases, variables and ports. A simplified example of the structured DEVS with the DEVS diagram shows the effectiveness of the proposed formalism which can be easily implemented in an objected-oriented simulation environment.

• Journal of the Korea Society for Simulation
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• v.22 no.4
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• pp.109-118
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• 2013

This paper adopts the system configuration to assess the reliability instead of making a fault tree (FT), which is a traditional method to analyze reliability of a certain system; this is the reliability block diagram (RBD) method. The RBD method is a graphical presentation of a system diagram connecting the subsystems of components according to their functions or reliability relationships. The equipment model for the reliability simulation is modeled based on the discrete event system specification (DEVS) formalism. In order to make various alternatives of target system, this paper also adopts the system entity structure (SES), an ontological framework that hierarchically represents the elements of a system and their relationships. To enhance the calculation time of reliability analysis, GPU-based accelerations are adopted to the reliability simulation.

• Proceedings of the Korea Society for Simulation Conference
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• 2005.05a
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• pp.100-105
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• 2005

Development of complex discrete event simulators requires cooperation between domain experts and modeling experts who involve the development. With the cooperation the domain experts derive user requirement and modeling experts transform the requirement to a simulation model. This paper proposes a method for consistency verification of simulation model in DEVS formalism against the user requirement in UML diagrams. It also presents an automated tool, called VeriDEVS, which implements the proposed method. Inputs of VeriDEVS are three UML diagrams, namely use case, class and sequence diagrams, and DEVS Graph, all in Visio; outputs of a verification result is represented in PowerPoint files.