• Journal of KIISE:Computer Systems and Theory
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• v.33 no.12
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• pp.867-879
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• 2006

This paper concerns fast and time accurate HW/SW cosimulation for MPSoC(Multi-Processor System-on-chip) architecture where multiple software and/or hardware components exist. It is becoming more and more common to use MPSoC architecture to design complex embedded systems. In cosimulation of such architecture, as the number of the component simulators participating in the cosimulation increases, the time synchronization overhead among simulators increases, thereby resulting in low overall cosimulation performance. Although SystemC cosimulation frameworks show high cosimulation performance, it is in inverse proportion to the number of simulators. In this paper, we extend the novel technique, called virtual synchronization, which boosts cosimulation speed by reducing time synchronization overhead: (1) SystemC simulation is supported seamlessly in the virtual synchronization framework without requiring the modification on SystemC kernel (2) Parallel execution of component simulators with virtual synchronization is supported. We compared the performance and accuracy of the proposed parallel SystemC cosimulation framework with MaxSim, a well-known commercial SystemC cosimulation framework, and the proposed one showed 11 times faster performance for H.263 decoder example, while the accuracy was maintained below 5%.

• Journal of Broadcast Engineering
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• v.15 no.4
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• pp.513-526
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• 2010

In this paper, we propose a de-blocking filter for improvement of coding efficiency and computational complexity reduction on a high definition video coding. Recently, the H.264/AVC standard-based research for high definition video coding method is under way because the amount of used of high definition videos is on the increase. The H.264/AVC de-blocking filter is designed for low bitrate video coding and it improves not only the subjective quality but also coding efficiency by minimizing the blocking artifact. However, the H.264/AVC de-blocking filter that strong filtering is performed is not suitable in a high definition video coding which occurs relatively low blocking artifact. Also, the conventional de-blocking filter has high computational complexity in decoder side. The computational complexity of the proposed method is reduced about maximum 8.8% than conventional method. Furthermore, the coding efficiency of the proposed method is about maximum 7.3% better than H.264/AVC de-blocking filter.

• Journal of the Korea Society of Computer and Information
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• v.15 no.4
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• pp.83-90
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• 2010

In wireless sensor networks, the data transmitted from the sensor nodes are susceptible to corruption by errors which caused of noisy channels and other factors. In view of the severe energy constraint in Sensor Networks, it is important to use the error control scheme of the energy efficiently. In this paper, we presented RS (Reed-Solomon) codes in terms of their BER performance and power consumption. RS codes work by adding extra redundancy to the data. The encoded data can be stored or transmitted. It could have errors introduced, when the encoded data is recovered. The added redundancy allows a decoder to detect which parts of the received data is corrupted, and corrects them. The number of errors which are able to be corrected by RS code can determine by added redundancy. The results of experiment validate the performance of proposed method to provide high degree of reliability in low-power communication. We could predict the lifetime of RS codes which transmitted at 32 byte a 1 minutes. RS(15, 13), RS(31, 27), RS(63, 57), RS(127,115), and RS(255,239) can keep the days of 173.7, 169.1, 163.9, 150.7, and 149.7 respectively. The evaluation based on packet reception ratio (PRR) indicates that the RS(255,239) extends a sensor node's communication range by up about 3 miters.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.1
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• pp.90-102
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• 2011

Recently, the grade of users using wireless communication services which transmits and re-transmits to the signal via the broadcasting satellite have a variety. However the ships not preparing of H.264 standard devices should not received the realtime data because the broadcasting stations have transmitted the compressed video data through the satellite communication. Therefore this paper proposes H.264 to MPEG-2 transcoding for the ships using MPEG-2 devices. Proposed method improves a speed and object quality in H.264 to MPEG-2 transcoding by analysis features of macroblock modes in H.264. In the Intra mode of P-frame, it proposes new method by computing coincidence proportion after comparing of Intra mode methods of H.264 and MPEG-2. In the Inter mode, it proposes a PMV(predictive motion vector) considering movement of motion vectors in H.264 decoder. we reuses a PMV directly as like the final MV in MPEG-2 encoder and refinements the MV after coincidence ratio comparing of variable motion vectors of H.264 and these of MPEG-2. The experimental results from proposed method show a considerable reduction in processing time, as much as 70% and 67% respectively, with a small objective quality reduction in PSNR.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.18-24
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• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.4
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• pp.108-115
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• 2009

In this paper, we propose a novel true-motion estimation technique supporting efficient frame error concealment for error-resilient video coding. In general, it is important to accurately obtain the true-motion of objects in video sequences for effectively recovering the corrupted frame due to transmission errors. However, the conventional motion estimation (ME) technique, which minimizes a sum of absolute different (SAD) between pixels of the current block and the motion-compensated block, does not always reflect the true-movement of objects. To solve this problem, we introduce a new metric called an absolute difference of motion vectors (ADMV) which is the distance between motion vectors of the current block and its motion-compensated block. The proposed ME method can prevent unreliable motion vectors by minimizing the weighted combination of SAD and ADMV. In addition, the proposed ME method can significantly improve the performance of error concealment at the decoder since error concealment using the ADMV can effectively recover the missing motion vector without any information of the lost frame. Experimental results show that the proposed method provides similar coding efficiency to the conventional ME method and outperforms the existing error-resilient method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.64-70
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• 2008

The H.264 standard is widely used due to the high compression rate and quality. The deblocking filter of the H.264 standard improves the quality of images by eliminating blocking artifacts of pictures, and it requires a lot of computation. We propose a new hardware architecture for the deblocking filter with pipelined architecture, 1-D filters which support both horizontal and vertical filtering and efficient memory management. Four memory blocks are configured for the efficient storage and access of the current macroblock and adjacent referenced sub-macroblocks, and the pixel data from the motion compensation unit can be transferred without waiting during the computation cycles of the deblocking filter. The number of computation cycles and the hardware area are reduced using the proposed architecture, and the performance of the H.264 decoder is improved. We design the deblocking filter using Verilog-HDL and implement using an FPGA. The designed deblocking filter can be used for decoding HD quality images at 77 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1A
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• pp.26-34
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• 2002

Mobile telecommunication systems such as IS-95 and IMT-2000 employ frame based communication using frames up to 20 msec in length and the receiving end has to store the whole frome before it is being processed. The size of the frame buffer ofter dominates those of the processing unit such as soft decision Viterbi decoder. The frame buffer for IMT-2000, for example, has to be increased 80 times as large as that of IS-95. One of the parameters deciding the number of bits in a frame will be obviously the number of bits in soft quantization. Start after striking space key 2 times. This paper has studied a new aspect of offset and quantization step size on BER performance and proposes a new 3-bit soft quantization algorithm which shows similar performance as that of 4-bit soft decision Viterbi receiver. The optimal offset values and step sizes for the other practical quantization levels ---16, 8, 4, 2--- have also been found. In addition, a new optimal symbol metric table has been devised which takes the accumulation value of various repeated signals and produces a rescaled 3-bit valu.tart after striking space key 2 times.

• Journal of the Korea Society of Computer and Information
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• v.13 no.7
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• pp.29-36
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• 2008

This paper proposes algorithm for the system that can search for an image of a frame unit, and we implement it. A system already inserts in images after generating the cord that mechanical decoding and identification are possible. We are independent of an external noise in a frame unit, and a system to propose at these papers can search for an image recorded by search condition to include recording date, recording time, a recording place or filming course etc. This system is composed by image insertion wealth to insert data to an image to data image code generation wealth, a frame generating data image code you apply a code generation rule to be fixed in order to express to a price to have continued like data entry wealth, GPS locator values and direction price receiving an image signal, image decoding signals and an image search signal to include search condition, and to have continuity from users each of an image. Also, image decoding we decipher about the noise that was already added from the outsides in a telerecording process, a copy process or storage processes inserted in images by real time, and searching image information by search condition. Consequently we implement decoder, and provide the early system that you use, and we easily insert data code among images. and we can search. and maximization can get precision regarding an image search and use satisfaction as we use algorithm to propose at these papers.