• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
• /
• pp.277-280
• /
• 2000

In this paper, we designed a turbo decoder using VHDL. To maximize effective free distance of the turbo code, we implemented pseudo random interleaver. A MAP(Maximum a posteriori) decoder is used as a primimary decoder. We avoided multiplication by using lookup tables(ROM). We expect that this small-sized turbo decoder is suitable for mobile communication. We simulated turbo decoder with Altera MAX+PLUS II.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권4호
• /
• pp.488-496
• /
• 2016

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1998년도 하계학술대회 논문집 G
• /
• pp.2470-2472
• /
• 1998

In this paper, we proposed the method to improve the performance of Viterbi decoder by applying Concatenated structure. Proposed decoder for Concatenated Code is designed with inner Viterbi decoder, block deinterleaver and outer Viterbi decoder. Inner Viterbi decoder (K=7, R=1/2) has 8-level soft decision, but outer decoder (K=7, R= 1/2) has 2-level hard decision. Applied interleaving scheme make decoder to have better BER performance in Concatenated code. The designed VLSI shares inner decoder with outer decoder. Because of sharing structure, complexity of decoder can be reduced to half. But it required about twice clock speed.

• 정보저장시스템학회:학술대회논문집
• /
• 정보저장시스템학회 2005년도 추계학술대회 논문집
• /
• pp.103-110
• /
• 2005

We present a powerful error control decoder which can be used in all of the commercial DVD systems. The decoder exploits the error information from the modulation decoder in order to increase the error correcting capability. We can identify that the modulation decoder in DVD system can detect errors more than $60\%$ of total errors when burst errors are occurred. In results, fur a decoded block, error correcting capability of the proposed scheme is improved up to $25\%$ more than that of the original error control decoder. In addition, the more the burst error length is increased, the better the decoder performance. Also, a pipeline-balanced RSPC decoder with a low hardware complexity is designed to maximize the throughput. The maximum throughput of the RSPC decoder is 740Mbps@100MHz and the number of gate counts is 20.3K for RS (182, 172, 11) decoder and 30.7K for RS (208, 192, 17) decoder, respectively

• 전기학회논문지P
• /
• 제58권4호
• /
• pp.623-626
• /
• 2009

In this paper, we applied new analog viterbi decoder to decode PR(1,2,2,1) signal for DVD and analyze the specific and signal characteristics. We implemented the parallel analog viterbi decoder and the convolution digital viterbi decoder(the digital PRML) utilizing the technology of analog parallel processing circuits. The proposed analog viterbi decoder can replace the conventional digital viterbi decoder by a new one. Our circuits design the low distortion and the high accuracy over the previous implementation. Through the parallel structure of the proposed viterbi decoder, we got the achievement of the decoding speed by the multiple times.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 하계종합학술대회 논문집
• /
• pp.938-941
• /
• 1999

In this paper, we designed a pipeline (15,9) Reed-solomon decoder. To compute the error locator polynomials, we used the Euclidean algorithm. This algorithm includes computation of inverse element. We avoided the inverse element calculation in this RS decoder by using ROMs. We designed this decoder using VHDL. Simulation results show that the designed decoder corrects three error symbols. We implemented this design through an Altera FPGA chip.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2000년도 하계학술대회 논문집 D
• /
• pp.3157-3159
• /
• 2000

Soft Output Viterbi Algorithm is modification of Viterbi algorithm to deliver not only the decoded codewords but also a posteriori probability for each bit. This paper presents SOVA decoder which can be used for component decoder of turbo decoder. We used two-step SMU architectures combined with systolic array traceback methods to reduce the complexity of the design. We followed the specification of CDMA2000 system for SOVA decoder design.

• 전기학회논문지
• /
• 제58권3호
• /
• pp.627-631
• /
• 2009

This paper presents a novel current steering cell matrix DAC(digital-to-analog converter) architecture to reduce decoder area. The current cell matrix of a existing architecture is selected by columns and lows thermometer code decoder of input bits. But The current cell matrix of a proposal architecture is divided 2n by the thermometer code decoder of upper input bits and are selected by the thermometer code decoder of middle and lower input bits. Because of this configuration, decoder numbers have increased. But the gate number that composed of decoder has decreased. In case of the designed 8 bit current steering cell matrix DAC, the gate number of decoder has decreased by about 55% in comparison with a existing architecture.

• ETRI Journal
• /
• 제42권6호
• /
• pp.912-921
• /
• 2020

Quantum-dot cellular automata (QCA) is an alternative complementary metal-oxide-semiconductor (CMOS) technology that is used to implement high-speed logical circuits at the atomic or molecular scale. In this study, an optimal 2-to-4 decoder in QCA is presented. The proposed QCA decoder is designed using a new formulation based on the MV32 gate. Notably, the MV32 gate has three inputs and two outputs, which is equivalent two 3-input majority gates, and operates based on cellular interactions. A multilayer design is suggested for the proposed decoder. Subsequently, a new and efficient 3-to-8 QCA decoder architecture is presented using the proposed 2-to-4 QCA decoder. The simulation results of the QCADesigner 2.0.3 software show that the proposed decoders perform well. Comparisons show that the proposed 2-to-4 QCA decoder is superior to the previously proposed ones in terms of cell count, occupied area, and delay.

• 정보처리학회논문지:소프트웨어 및 데이터공학
• /
• 제9권12호
• /
• pp.419-430
• /
• 2020

본 연구는 기존 전력량 예측 모델의 구조를 변경하여 모델의 예측 능력을 향상 시킬 수 있는 방법에 관하여 연구하였다. 전기에 대한 수요는 그 어느 때보다 증가하고 있다. 산업 부문에서는 그 어느 부문 보다 전기 소모량이 많음으로, 더욱 정확한 공장 지역의 전력량 소모 예측 모델이 잉여 에너지 생산을 줄이기 위해 주목을 받고 있다. 우리는 2개의 개별 encoder와 한개의 decoder를 사용하여, 장기와 단기 데이터를 모두 사용하는 double encoder-decoder 모델을 제안한다. 우리는 제안된 모델을 세홍(주)의 생산 구역에서 2019년 1월 1일부터 2019년 6월 30일 까지 모집된 전력 소모량 데이터에서 평가 하였다. double encoder-decoder 모델은 기존의 encoder-decoder 모델을 사용했을 때와 비교하여 약 10 %의 평균 절대 비율 오차의 감소를 기록 하였다. 본 결과는 제안한 모델이 encoder-decoder 모델에 비해 생산 지역의 전력 사용량의 예측을 더 정확하게 하는 모델임을 보여준다.