• Journal of Photoscience
• /
• v.9 no.2
• /
• pp.240-242
• /
• 2002

In Drosophila melanogaster, it is known that the circadian clock consists of an autoregulatory feedback loop, which includes so-called clock genes, such as per, tim, dClk and cyc and produces periodical expression of per. It is recently suggested, however, that the circadian oscillation without the rhythmical expression of per is involved in the regulation of circadian locomotor rhythms. In the present study, we examined the existence and the property of the possible per-less oscillation using arrhythmic clock mutant flies carrying per$^{01}$, tim$^{01}$, dClk$^{Jrk}$ or cyc$^{01}$. When temperature cycles consisting of 25$^{\circ}$Ｃ and 30$^{\circ}$Ｃ with varying periods (T = 8~32 hr) were given, they showed rhythms synchronizing with the given cycle under constant darkness (DD). per$^{01}$ and tim$^{01}$ flies always showed a peak around 7 hr after the onset of thermophase irrespective of Ts of temperature cycles, while dClk$^{Jrk}$ and cyc$^{01}$ flies did not. In addition, several days were necessary to establish a clear temperature entrainment in per$^{01}$ and tim$^{01}$ flies, when they were transferred from a constant temperature to a temperature cycle under DD. These results suggest that per$^{01}$ and tim$^{01}$ flies have a temperature-entrainable weak oscillatory mechanism. The fact that dClk$^{Jrk}$ and cyc$^{01}$ flies did not show any sign of the endogenous oscillation suggests that the per-less oscillatory mechanism may require CLK and CYC.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 1999.11a
• /
• pp.161-166
• /
• 1999

The global trends of mobile communication system is moving toward digitizing, high-speed and large-capacity. Also, to utilize the limited frequency-resource efficiently, spread spectrum system is a mainstream. In this study we are concerning with the fast frequency-hopping system. Instead of the PLL with many problems such as phase-noise, we used the DDS is popular in these days minimizes the disadvantage of PLL. In the case the FFH system is designed using the PLL, it is difficult to be satisfied of the design conditions such as RF badwidth and the settling time of PLL, and it has limitation because of complex circuit by using the balanced modulator. In this study, we evaluated the performance in order to design the FFH system using the DDS. The system that has the improvement of error rate, 1Mhps hopping rate and 5MHz RF bandwidth is designed and evaluated.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.9A
• /
• pp.729-736
• /
• 2005

In this paper, we introduce a new approach for the design of uplink sub-channel allocation and power control in the High-speed Portable Internet system that is based on OmMAnDD scheme. In OFDMA system, because the number of allocated sub-channel in mobile station varies from one to the whole sub-channel as in base station while mobile station's transmit power is lower than that of base station, full loading range(FLR) constraint occurs where whole sub-channel can be used and the conventional open-loop power control scheme can not be used beyond FLR. We propose a new scheme that limits the maximum sub-channel allocation number and uses power concentration gain(PCG) depending on location of mobile station, which is based on ranging in OfDMA system. Simulation results show that the proposed scheme extends the uplink coverage to the entire cell service coverage area, provides solutions for optimum utilization of radio resource and enables open-loop power control beyond FLR without extra hardware complexity.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.3 no.4
• /
• pp.805-817
• /
• 1999

In this paper, the needs for introduction and adoption of MㆍHF DSC/NBDP system and for developments of its circuits and call sequences for use in the maritime mobile services for small-ships, leisure-ships and fishing ships are analyzed, discussed. Also design and implement for MㆍHF(1.6-4MHz) DSC/NBDP system is discussed. Most of casualties have been arisen from small-ships and fishing ships during last 5 years. So, the SAR schematic plans should been prepared to prevent casualties and facilitate the activities of SAR for those ships. DSC/NBDP for MㆍHF system is able to fulfill the roles of efficient SAR communication functions, and to advance the SAR system to small ships and fishing ships. This study is focused on the techniques of processing the DSC call sequences and the ARQ sequences of NBDP system. Especially ARQ sequences are expanded into processing of Korean letters, designed the call sequences and code conversion algorithm for Korean-code. It will be evaluated the availability of Korean-NBDP system. In designing the Transmitting circuits and Receiving circuits, for the carrier generation, DDS(Direct Digital Synthesizer) is used in stead of the Phase Locked Loop and frequency conversion by the mixer, BPF. And PSK modulation signals are directly generated by the controls of DDS, which show the characteristics of Spurious Free Dynamic Range are below -62dBc. Also, the monolithic U subsystem IC which provides various functional components, AD608 is used for designing the receiving circuitsㆍAnd the algorithm of Phasing methode for FSK demodulation are devised to process IF frequency 455kHz in the IF circuits.

• Journal of Internet Computing and Services
• /
• v.24 no.5
• /
• pp.37-50
• /
• 2023

In general, PLL or DDS are mainly used as precise and stable frequency synthesis methods. For stable operation, a PWM frequency generation algorithm was designed and implemented using FPGA. This is an algorithm that creates a frequency 8,192 times the target frequency and then performs the D flip-flop 13 times to generate multiple frequencies with a precision of 1 Hz. Using the designed algorithm, it is applied to the Berthing system for stopping trains in station. The applied product was developed and tested against the existing operating system to confirm its superior performance in terms of frequency generation accuracy.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1093-1096
• /
• 2003

본 논문에서는, CMOS APS Image Sensor 내에 포함되어 회로의 면적을 줄인 새롭게 제안된 CMOS Bandgap Reference Bias Generator (BGR)를 온도 및 방사능에 대한 응답을 실험하였다. 제안된 BGR 회로의 설계 목표는 V/sub DD/는 2.5V이상이고, V/sub ref/는 0.75V ± 0.5mV 마진을 가지게 하는 것이다. 제안된 BGR회로는 Level Shifter를 갖는 Differential OP-amp단과 Feedback-Loop를 가지는 Cascode Current Mirror를 사용하여 저전압에서도 동작을 가능하게 하였으며, 높은 출력저항 특성을 가지도록 하였다. 제안된 BGR회로는 하이닉스 0.18㎛ ( triple well two-poly five-metal ) CMOS 공정을 이용하여 Test Chip을 제작하였다. 온도의 변화와 Co-60 노출조건 하에서 Total ionization dose (TID) effect된 BGR회로의 V/sub ref/를 측정하여, 이를 평가하였다. 온도에 대한 반응은, 25℃ 일 때의 V/sub ref/에 대해, 각각 45 ℃에서 0.128%. 70℃에서 0.768% 변화하였다. 그리고 온도가 25℃일 때 50krad와 100krad의 방사능을 조사 하였을 경우, V/sub ref/는 각각 2.466%, 그리고 4.612% 변화하였다.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.12 no.5
• /
• pp.1-9
• /
• 2012

In this paper, we presents the modeling and implementation of the DDS(Direct Digital synthesizer) driven offset PLL(Pghase Locked Loop) with DAC(Digital Analog Converter) for coarse tune. The PLL synthesizer was designed for minimizing the size and offset frequency and DDS technique was used for ultra low noise and fast lock up time, also DAC was used for coarse tune. The output phase noise was analyzed by superposition theory with the phase noise transfer function and noise source modeling. the phase noise prediction was evaluated by comparing with the measured data. The designed synthesizer has ultra fast lock time within 6 usec and ultra low phase noise performance of -120 dBc/Hz at 10KHz offset frequency.

• Journal of Life Science
• /
• v.22 no.8
• /
• pp.999-1008
• /
• 2012

The circadian clock is a self-sustaining 24-hour timekeeper that allows organisms to anticipate daily-changing environmental time cues. Circadian clock genes are regulated by a transcriptional-translational feedback loop. In Arabidopsis, LATE ELONGATED HYPOCOTYL (LHY) and CIRCADIAN CLOCK-ASSOCIATED 1 (CCA1) transcripts are highly expressed in the morning. Translated LHY and CCA1 proteins repress the expression of the TIMING OF CAB EXPRESSION 1 (TOC1) transcripts, which peaks in the evening. The TOC1 protein elevates the expression of the LHY and CCA1 transcripts, forming a negative feedback loop that is believed to constitute the oscillatory mechanism of the clock. In mammals, the transcription factor protein CLOCK, which is a central component of the circadian clock, was reported to have an intrinsic histone acetyltransferase (HAT) activity, suggesting that histone acetylation is important for core clock mechanisms. However, little is known about the components necessary for the histone acetylation of the Arabidopsis clock-related genes. Here, I report that DET1 (De-Etiolated1) functions as a negative regulator of a key component of the Arabidopsis circadian clock gene LHY in constant dark phases (DD) and is required for the down-regulation of LHY expression through the acetylation of histone 3 (H3Ac). However, the HATs directly responsible for the acetylation of H3 within LHY chromatin need to be identified, and a link connecting the HATs and DET1 protein is still absent.