• Title/Summary/Keyword: DCT/IDCT Architecture

Search Result 3, Processing Time 0.136 seconds

A Low-Power 2-D DCT/IDCT Architecture through Dynamic Control of Data Driven and Fine-Grain Partitioned Bit-Slices (데이터에 의한 구동과 세분화된 비트-슬라이스의 동적제어를 통한 저전력 2-D DCT/IDCT 구조)

  • Kim Kyeounsoo;Ryu Dae-Hyun
    • Journal of Korea Multimedia Society
    • /
    • v.8 no.2
    • /
    • pp.201-210
    • /
    • 2005
  • This paper proposes a power efficient 2-dimensional DCT/IDCT architecture driven by input data to be processed. The architecture achieves low power by taking advantage of the typically large fraction of zero and small-valued input processing data in video and image data compression. In particular, it skips multiplication by zero and dynamically activates/deactivates required bit-slices of fine-grain bit partitioned adders within multipliers and accumulators using simple input ANDing and bit-slice MASKing. The processed results from 1-D DCT/IDCT do not have unnecessary sign extension bits (SEBs), which are used for further power reduction in matrix transposer. The results extracted by bit-level transition activity simulations indicate significant power reduction compared to conventional designs.

  • PDF

High Speed 2D Discrete Cosine Transform Processor

  • Kim, Ji-Eun;Hae Kyung SEONG;Kang Hyeon RHEE
    • Proceedings of the IEEK Conference
    • /
    • /
    • pp.1823-1826
    • /
    • 2002
  • On modern computer culture, the high quality data is required in multimedia systems. So, the technology of data compression fur data transmission is necessary now. This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT (Discrete Cosine Transform/Inverse Discrete Cosine Transform. In the proposed architecture, the area of hardware is reduced by using the DA (distributed arithmetic) method and applies the concepts of pipeline to the parallel architecture. As a result the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared with the non-pipeline architecture.

  • PDF

Design on Pipeline Architecture for the Low and Column Address Generator of 2D DCT/IDCT (2D DCT/IDCT의 행, 열 주소생성기를 위한 파이프라인 구조 설계)

  • 노진수;박종태;문규성;성해경;이강현
    • Proceedings of the Korea Multimedia Society Conference
    • /
    • /
    • pp.14-18
    • /
    • 2003
  • This paper presents the pipeline architecture for the low and column address generator of 2D DCT/IDCT(Discrete Cosine Transform/Inverse Discrete Cosine Transform). For the real time process of image data, it is required that high speed operation and small size hardware In the proposed architecture, the area of hardware is reduced by using the DA(distributed arithmetic) method and applying the concepts of pipeline on the parallel architecture. As a results, the designed pipeline of the low and column address generator for 2D DCT/IDCT architecture is implemented with an efficiency and high speed compared as the non-pipeline architecture. And the operation speed is improved about 50% up. The design for the proposed pipeline architecture of DCT/IDCT is coded using VHDL.

  • PDF