• Journal of Power Electronics
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• 제16권5호
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• pp.1928-1938
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• 2016

The three-phase four-wire shunt active power filter (APF) is an effective method to solve the harmonic problem in three-phase four-wire power systems. In addition, it has two possible topologies, a four-leg inverter and a three-leg inverter with a split-capacitor. There are some studies investigating DC-link voltage control in three-phase four-wire APFs. However, when compared to the four-leg inverter topology, maintaining the balance between the DC-link upper and lower capacitor voltages becomes a unique problem in the three-leg inverter with a split-capacitor topology, and previous studies seldom pay attention to this fact. In this paper, the influence of the balance between the two DC-link voltages on the compensation performance, and the influence of the voltage balance controller on the compensation performance, are analyzed. To achieve the balance between the two DC-link capacitor voltages, and to avoid the adverse effect the voltage balance controller has on the APF compensation performance, a new DC-link voltage balance control strategy for the three-phase four-wire split-capacitor APF is proposed. Representative simulation and experimental results are presented to verify the analysis and the proposed DC-link voltage balance control strategy.

• Journal of Power Electronics
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• 제19권1호
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• pp.108-118
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• 2019

This paper proposes a DC-link voltage balance controller using the fourth-phase of a three-level neutral-point clamped (NPC) PWM converter with medium vector selection (MVS) PWM for common-mode voltage reduction. MVS PWM makes the voltage reference by synthesizing the voltage vectors that cannot generate common-mode voltage. This PWM method is effective for reducing the EMI noise emitted from converter systems. However, the DC-link voltage imbalance problem is caused by the use of limited voltage vectors. Therefore, in this paper, the effect of MVS PWM on the DC-link voltage of a three-level NPC converter is analyzed. Then a proportional-derivative (PD) controller for the DC-link voltage balance is designed from the DC-link modeling. In addition, feedforward compensation of the neutral point current is included in the proposed PD controller. The effectiveness of the proposed controller is verified by experimental results.

• Journal of Power Electronics
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• 제11권6호
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• pp.811-818
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• 2011

Modulation strategies for multilevel inverters have typically focused on synthesizing a desired set of sinusoidal voltage waveforms using a fixed number of dc voltage sources. This makes the average power drawn from different dc voltage sources unequal and time varying. Therefore, the dc voltage sources are unregulated and require that corrective control action be incorporated. In this paper, first two new selections are proposed for determining the dc voltage sources values for asymmetric cascaded multilevel inverters. Then two modulation strategies are proposed for the dc power balancing of these types of multilevel inverters. Using the charge balance control methods, the power drawn from all of the dc sources are balanced except for the dc source used in the first H-bridge. The proposed control methods are validated by simulation and experimental results on a single-phase 21-level inverter.

• Journal of Power Electronics
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• 제12권1호
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• pp.88-97
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• 2012

This paper presents a method for the digital control of a high power factor AC/DC converter employing the power balance control technique to achieve a fast response of the output voltage control. To avoid the effects of an output voltage ripple in the voltage control loop, the average output voltage is sampled and used as a feedback signal for the output voltage controller. The proposed control technique was verified by simulations using MATLAB/Simulink and its implementation was realized by a dsPIC30F4011 digital signal processor to control a CUK topology AC/DC converter with a 48V output voltage and a 250 W output power. The experimental results agree with the simulation results. The proposed control technique achieves a fast transient response with a lower line current distortion than is achieved when using a conventional proportional-integral controller and the power balance control technique with the conventional sampling method.

• Journal of Power Electronics
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• 제19권2호
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• pp.560-568
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• 2019

This paper studies the inherent relationship between currents and zero-sequence components. Then a precise algorithm is proposed to calculate the injected zero-sequence component to control the DC-Link neutral-point voltage balance, which can result in a more efficient and flexible neutral point voltage balance with a desirable performance. In addition, it is shown that carried-based PWM with the calculated zero-sequence component scheme can be equivalent to space-vector pulse-width modulation (SVPWM). Based on the proposed method, the optimal zero-sequence component of the feasible modulation indices is analyzed. In addition, the unbalanced load limitation of the DC-Link neutral-point voltage balance control is also revealed. Simulation and experimental results are shown to verify the validity and practicality of the proposed algorithm.

• Journal of Power Electronics
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• 제12권5호
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• pp.739-747
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• 2012

This paper applies carrier phase shifted pulse-width modulation (CPS-PWM) to transformerless modular multilevel converters (MMC) to improve the output spectrum. Because the MMC topology is characterized by the double-star connection of six legs consisting of cascaded modular chopper cells with floating capacitors, the balance control of the DC-link capacitor voltage is essential for safe operation. This paper presents a leg-balancing control strategy to achieve DC-link voltage balance under all operating conditions. This strategy based on circulating current decoupling control focused on DC-link balancing between the upper and lower legs in each phase pair by considering the six legs as three independent phase-pairs. Experiments are implemented on a 100-V 3-kVA downscaled prototype. The experimental results show that the proposed leg-balancing control is both effective and practical.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2224-2236
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• 2014

The performance of an isolated high voltage full bridge converter is improved using a voltage doubler. In a conventional high voltage full bridge converter, the diode of the transformer secondary voltage undergoes a voltage spike due to the leakage inductance of the transformer and the resonance occurring with the parasitic capacitance of the diode. In addition, in the phase shift control, conduction loss largely increases from the freewheeling mode because of the circulating current. The efficiency of the converter is thus reduced. However, in the proposed converter, the high voltage dual converter consists of a voltage doubler because the circulating current of the converter is reduced to increase efficiency. On the other hand, in the proposed converter, an input current is distributed when using parallel input / serial output and the output voltage can be doubled. However, the voltages in the 2 serial DC links might be unbalanced due to line impedance, passive and active components impedance, and sensor error. Considering these problems, DC injection is performed due to the complementary operations of half bridge inverters as well as the disadvantage of the unbalance in the DC link. Therefore, the serial output of the converter needs to control the balance of the algorithm. In this paper, the performance of the conventional converter is improved and a balance control algorithm is proposed for the proposed converter. Also, the system of the 1.5[kW] PCS is verified through an experiment examining the operation and stability.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.576-588
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• 2014

The superiority of CMI (Cascaded Multilevel Inverter) is unparalleled in high power and high voltage STATCOM (Static Synchronous Compensator). However, the parameters and operating conditions of each individual power unit composing the cascaded STATCOM differ from unit to unit, causing unit voltage disequilibrium on the DC side. This phenomenon seriously impairs the operation performance of STATCOM, and thus maintaining the DC voltage balance and stability becomes critical for cascaded STATCOM. This paper analyzes the case of voltage disequilibrium, combines the operation characteristics of the cascaded STATCOM, and proposes a new DC voltage control scheme with the advantages of good control performance and stability. This hierarchical control method uses software to achieve the total active power control and also uses chopper controllers to enable that the imbalance power can flow among the capacitors in order to keep DC capacitor voltages balance. The operating principle of the chopper controllers is analyzed and the implementation is presented. The major advantages of the proposed control strategy are that the number of PI regulators has been decreased remarkably and accordingly the blindness of system design and debugging also reduces obviously. The simulation reveals that the proposed control scheme can achieve the satisfactory control goals.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.316-317
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• 2018

This paper propse the DC link capacitor voltage balancing control for three level neutral point clamped converter with harmonic component injection method. The injcetion voltage consists of harmonic component and DC link capacitor voltage difference. Theoretical analysis is provided to balance the DC link voltage, and it shows that harmonic component compensates the unbalanced condition between the capacitors. Both simulations and experiments are carried out to show that the voltage unbalance have been decreased by the proposed method.

• Journal of Power Electronics
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• 제17권3호
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• pp.664-673
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• 2017

With the development of multilevel converters, cascaded single-phase H-bridge rectifiers (CHBRs) has become widely adopted in high-voltage high-power applications. In this study, sequence pulse modulation (SPM) is proposed for CHBRs. SPM is designed to balance the dc-link voltage and maintain the smooth changes of switch states. In contrast to phase disposition modulation, SPM balances the dc-link voltage even after removing the load of one submodule. The operation principle of SPM is deduced, and the unbalance degree of SPM is analyzed. All the proposed approaches are experimentally verified through a prototype of a four-module (nine-level) CHBR. Conclusions are drawn in accordance with the results of SPM and its imbalance degree analysis.