• Publications of The Korean Astronomical Society
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• v.11 no.1
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• pp.109-123
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• 1996

We have developed a 5GHz continuum receiver system. The receiver is a direct type receiver. In order to reduce the noise due to the fluctuation of the gain in the amplifiers, the system employs the Dicke switching method. We made the 5GHz low-noise amplifier and the bandpass filter. The low-noise amplifier gives ${\sim}35dB$ gain and has ${\sim}210K$ noise temperature. The bandpass filter has a passband between 4.3 and 5.4GHz. We also made switch driver, video amplifiers, phase detector, and integrator. Using a 1.8 meter offset parabolic antenna, we measured the efficiency of the system. Since the antenna does not have a driver to track objects, observations were performed with the antenna fixed. The measured noise temperature of the system is ${\sim}650K$. From the observation of the blank sky, noise level was measured. It was found that the systematic noise(${\sim}0.5K$: peak to peak value) is much larger than the thermal noise. The systematic noise is possibly related to the stability of the DC power supplied to the receiver system. Besides the noise of the system, it was found that the airplanes are the very serious noise sources. We measured the radio flux of the Sun using the developed system. The observed radio flux of the Sun is ${\sim}10^6Jy$, which is close to the known value of the quiet Sun. The test observation of the Sun shows that the angular beam size of the antenna is ${\sim}2.2^{\circ}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.19-27
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• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.5
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• pp.471-482
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• 2015

In this paper, design and implementation of the 94 GHz Gunn oscillator and the evaluation of the maximum power of the Gunn diode used in the oscillator are presented. The 94 GHz Gunn oscillator is used InP Gunn diode and designed employing a WR-10 waveguide. The designed oscillator is fabricated through machining and its performance is measured. The fabricated oscillator shows an oscillation frequency of 95 GHz, output power of 12.64 dBm, and phase noise of -92.7 dBc/Hz at 1 MHz offset frequency. To evaluation the maximum power of the InP Gunn diode used in oscillator, the oscillator structure is modified to a structure having a diaphram. The height of thick diaphram which is used in the oscillator is varied. As a result, an oscillator has several different load impedances, which makes it possible to plot $G_L-V^2$ plot at the post plane. Using the $G_L-V^2$ plot, the maximum power of used Gunn diode including post is computed to be 16.8 dBm. Furthermore using the shorted and zero bias Gunn diode, the post loss used for DC biasing can be computed. Using the two losses, The maximum power of a InP Gunn diode is computed to be 18.55 dBm at 95 GHz. This result is close to a datasheet.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.4
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• pp.418-425
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• 2014

This paper presents a Ku-Band Doppler Radar System to measure respiration and heart rate. It was measured by using simultaneous radar and ECG(Electrocardiogram). Arctangent demodulation without dc offset compensation can be applied to transmitted I/Q(In-phase & Quadrature-phase) signal in order to improve the RMSE(Root Mean Square Error) about 50 %. The power leaked to receiving antenna from the transmitting antenna is always generated because of continuously opening the transceiver of CW(Continuous Wave) Doppler radar. As the output power increase, leakage power has an effect on the SNR(Signal-to-Noise Ratio) of the system. Therefore, in this paper, leakage cancellation technique that adds the signal having the opposite phase of the leakage power to the leakage power was implemented in order to minimize the decline of receiver sensitivity. By applying the leakage cancellation techniques described above, it is possible to measure the heart rate and respiration of the human at a distance of up to 35 m. the heart rate of the measured data at a distance of 35 m accords with the heart rate extracted from the ECG data.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.152-158
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• 2004

A low phase noise frequency synthesizer at X-Band which employs the subharmonic injection locking was designed and tested. The designed frequency synthesizer consists of a 1.75 GHz master oscillator - which also operates as a harmonic generator - and a 10.5 GHz slave oscillator. A 1.75 GHz master oscillator based on PLL technique used two transistors - one constitutes the active part of VCO and the other operates as a buffer amplifier as well as harmonic generator. The first stage operates a fixed locked oscillator and using the BJT transistor whose cutoff frequency is 45 GHz, the second stage is designed, operating as a harmonic generator. The 6th harmonic which is produced from the harmonic generator is injected into the following slave oscillator which also behaves as an amplifier having about 45 dB gain. The realized frequency synthesizer has a 7.4 V/49 mA, -0.5 V/4 mA of the low DC power consumption, 4.53 dBm of output power, and a phase noise of -95.09 dBc/Hz and -108.90 dBc/Hz at the 10 kHz and 100 kHz offset frequency, respectively.