• 한국태양에너지학회 논문집
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• 제37권6호
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• pp.1-12
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• 2017

The DC link of Grid-Connected 3-Phase 3-Level T-type Photovoltaic PCS (PV-PCS) consists of two series connected capacitors for using their neutral voltage. The mismatch between two capacitor characteristics and transient states happened in load change cause the imbalance of neutral voltage. As a result, PV-PCS performance is degraded and the system becomes unstable. In this paper, a mathematical model for analyzing the imbalance of neutral voltage is derived and a compensation method using offset voltage is proposed, where offset voltage adjusts the applying time of P-type and N-type small vectors. The validity of the proposed methods is verified by simulation and experiment.

• Journal of electromagnetic engineering and science
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• 제17권2호
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• pp.98-104
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• 2017

This work describes the development and comparison of two phase-locked loops (PLLs) based on a 65-nm CMOS technology. The PLLs incorporate two different topologies for the output voltage-controlled oscillator (VCO): LC cross-coupled and differential Colpitts. The measured locking ranges of the LC cross-coupled VCO-based phase-locked loop (PLL1) and the Colpitts VCO-based phase-locked loop (PLL2) are 119.84-122.61 GHz and 126.53-129.29 GHz, respectively. Th e output powers of PLL1 and PLL2 are -8.6 dBm and -10.5 dBm with DC power consumptions of 127.3 mW and 142.8 mW, respectively. Th e measured phase noise of PLL1 is -59.2 at 10 kHz offset and -104.5 at 10 MHz offset, and the phase noise of PLL2 is -60.9 dBc/Hz at 10 kHz offset and -104.4 dBc/Hz at 10 MHz offset. The chip sizes are $1,080{\mu}m{\times}760{\mu}m$ (PLL1) and $1,100{\mu}m{\times}800{\mu}m$ (PLL2), including the probing pads.

• 한국항공우주학회지
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• 제41권1호
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• pp.79-84
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• 2013

DC/DC 컨버터는 임의의 직류전원을 부하가 요구하는 형태의 직류전원으로 변환시키는 효율이 높은 전력변환기이다. DC/DC 컨버터는 PWM-IC(펄스폭 변조 집적회로) 제어기, MOSFET(산화물-반도체 전계 효과 트랜지스터), 인덕터, 콘덴서 등으로 구성되어있다. 코발트 60 ($^{60}Co$) 저준위 감마발생기를 이용한 TID실험에서 방사선의 영향으로 PWM-IC의 전기적 특성중에 문턱전압과 옵셋전압이 증가되고, SEL에 적용된 4종류의 중이온 입자는 PWM-IC의 파형을 불안정하게 만든다. 또한, 입/출력관계의 파형을 SPICE 시뮬레이션 프로그램으로 관찰하였다. PWM-IC의 TID 실험은 30 Krad 까지 수행하였으며, SEL 실험을 제어보드를 구현한 후 LET($MeV/mg/cm^2$)별 cross section($cm^2$)으로 연구하였다.

• 센서학회지
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• 제14권5호
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• pp.350-356
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• 2005

We have developed a dual-channel type automatic measurement system to evaluate AC-DC current transfer difference of the thermal current converter(TCC) which is primary standard of AC current. The output drift effect of the TCC is minimized by measuring simultaneously the output voltages of two TCCs using voltmeter. Furthermore, the offset voltage of the voltmeter is cancelled nearly out by taking the average values of two outputs of TCCs measured with the forward-reverse directions using dual channel scanner. The uncertainties of the automatic system were 7 to $86{\mu}A/A$ for 3 mA to 10 A at 40 Hz to 20 kHz, which were evaluated by the comparisons between adjacent range of TCCs and inter-comparison with national measurement institute of Germany(PTB). The capability for ac-dc transfer difference measurement was improved by one order compared with that for the manual ac-dc measurement system.

• ETRI Journal
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• 제36권1호
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• pp.12-21
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• 2014

In this paper, we propose a new digital blind in-phase/quadrature-phase (I/Q) mismatch compensation technique for image rejection in a direct-conversion receiver (DCR). The proposed image-rejection circuit adopts DC offset cancellation and a sign-sign least mean squares (LMS) algorithm with a unique step size adaptation both for a fast and precise I/Q mismatch estimation. In addition, several performance-optimizing design considerations related to accuracy, speed, and hardware simplicity are discussed. The implementation of the proposed circuit in an FPGA results in an image-rejection ratio (IRR) of 65 dB, which is the best performance with modulated signals, along with an adaptation time of 0.9 seconds, which is a tenfold increase in the compensation speed as compared to previously reported circuits. The proposed technique will be a promising solution in the area of image rejection to increase both the speed and accuracy of future DCRs.

• Journal of Power Electronics
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• 제18권5호
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Journal of Power Electronics
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• 제6권3호
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• pp.235-244
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• 2006

Recently, speed sensorless vector control for synchronous reluctance motors (SYRMs) has deserved attention because of its advantages. Although rotor angle calculation using flux estimation is a straightforward approach, the DC offset can cause an increasing pure integrator error in this estimator. In addition, this method is affected by parameter fluctuation. In this paper, to control the motor at the low speed region, a modified programmable cascaded low pass filter (MPCPLF) with sensorless online parameter identification based on a block pulse function is proposed. The use of the MPCLPF is suggested because in programmable, cascade low pass filters (PCLPF), which previously have been applied to induction motors, the drift increases vastly wl)en motor speed decreases. Parameter identification is also used because it does not depend on estimation accuracy and can solve parameter fluctuation effects. Thus, sensorless speed control in the low speed region is possible. The experimental system includes a PC-based control with real time Linux and an ALTERA Complex Programmable Logic Device (CPLD), to acquire data from sensors and to send commands to the system. The experimental results show the proposed method performs well, speed and angle estimation are correct. Also, parameter identification and sensorless vector control are achieved at low speed, as well as, as at high speed.

• International journal of advanced smart convergence
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• 제10권1호
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• pp.12-23
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• 2021

This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.

• 한국전자파학회논문지
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• 제16권6호
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• pp.603-614
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• 2005

본 논문에서는 CQPSK(Compatible QPSK) 변조 방식을 이용하여 APCO P25 규격을 만족하는 직접 변환 방식 디지털 초협대역 무전기를 구현하였다. 초협대역화에 따른 DC-offset 및 AC-coupling 영향, CQPSK 변조 방식에 대한 전력 증폭기의 비선형 특성을 최소화하기 위한 무전기 RF 트랜시버 설계 및 제작 방안을 제시하였다. 직접 변환 방식 RE 트랜시버 및 DSP 모듈과의 연동 시험 결과 송신기의 경우 36.8 dBm의 PEP에서 FCC 방사 마스크 규격을 만족하였다. PWM 제어 신호에 의한 수신기 AGC 동작 범위는 40 dB 범위에서 선형적으로 동작 하였고, 수신 감도 레벨(-116 dBm)에서도 양호한 음성 통화가 가능하였다. 또한 입력 SNR에 따른 BER 성능 및 주파수 오프셋 변화에 대한 BER 성능 측정 결과 무전기 성능 요구 규격을 만족함을 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.567-570
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• 1996

A predictive current control technique for an induction motor employing a resonant DC link inverter is proposed to overcome the disadvantage of the current regulated delta modulation(CRDM) which was employed to control the resonant DC link inverter. The discrete model of an induction motor and estimation of back EMF are investigated and a novel predictive current control technique is newly developed based on this discrete model and estimated back EMF. Using the proposed control technique, the minimized current ripple with reduced offset can be obtained. The usefulness of the proposed technique is verified through the computer simulation.