• 전력전자학회:학술대회논문집
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• 전력전자학회 2020년도 전력전자학술대회
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• pp.79-81
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• 2020

임계모드 (Critical conduction mode, CrM) 동작을 하는 PFC 컨버터는 주파수 변동을 통한 Valley switching 동작으로 인하여 높은 효율 및 양호한 EMI 특성을 가진다. 하지만 Peak 부하가 큰 시스템에서 CrM 설계를 하게 되면 정격부하에서 비교적 높은 주파수의 동작이 불가피하여 시스템 효율이 나빠지고 높은 DC-bias 확보를 위해 인덕터 크기가 커지게 된다. 따라서 본 논문에서는 고효율 및 인덕터 사이즈 저감을 위한 임계모드에서 동작하는 두 개의 교차형 PFC 컨버터의 병렬 구동에 대해서 이야기하고자 한다.

• 센서학회지
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• 제7권6호
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• pp.401-408
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• 1998

교류전압표준기인 열전형 전압변환기의 교류-직류 변환오차를 비교평가하기 위하여 이중채널방식 자동측정시스템을 개발하였다. 비교측정되는 2대의 변환기출력을 동시에 측정하여 드리프트의 영향을 감소시켰고, 또 저열기전력 이중채널 스캐너를 사용하여 변환기 출력을 순방향-역방향으로 측정하여 그 평균값을 취함으로서 전압측정기의 ���V전압이 제거되도록 하였다. 정격전압이 동일한 4 V인 변환기끼리 비교 측정한 결과, 주파수 $40\;Hz{\sim}100\;kHz$에서는 외국표준기관에서의 측정값과 약 ${\pm}2\;ppm$ 이내에서 일치하였으며, $200\;kHz{\sim}1\;MHz$ 범위에서는 약 ${\pm}4\;ppm$ 이내에서 일치하였다. 본 시스템의 개발로 변환기의 교류-직류 변환오차의 측정능력을 기존수동방식의 약 ${\pm}15\;ppm$에서 ${\pm}\;3ppm$(100 kHz 이하)로 크게 향상시켰으며, 표준유지 및 산업체 지원의 효율을 크게 높일 수 있게 되었다.

• 전력전자학회논문지
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• 제12권6호
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• pp.433-440
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• 2007

에너지 절약과 환경 문제가 이슈화되면서 대표적인 전원공급장치인 SMPS의 대기모드 효율이 중요시되고 있다. 특히 많은 SMPS들이 다출력 구조로 설계됨에 따라 대기모드에서 전력손실을 줄이기가 쉽지 않다. 본 논문에서는 SSPR(Secondary Side Post Regulator)을 개발하여 단일 컨버터에서 Cross Regulation과 대기전력을 함께 해결하였다. 그리고, 다중 컨버터의 대기전력 감소를 위하여 전류모드 제어와 Power Sequence 제어기술을 제안한다. 제안된 기술은 이론적 해석과 더불어 120[W], 270[W]급 SMPS에 적용하여 그 타당성 및 우수성을 검증하였다.

• Journal of Electrical Engineering and Technology
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• 제9권1호
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• pp.143-153
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• 2014

This paper presents a novel application of LCC resonant converter for 60kW EV fast charger and describes development of the high efficiency 60kW EV fast charger. The proposed converter has the advantage of improving the system efficiency especially at the rated load condition because it can reduce the conduction loss by improving the resonance current shape as well as the switching loss by increasing lossless snubber capacitance. Additionally, the simple gate driver circuit suitable for proposed topology is designed. Distinctive features of the proposed converter were analyzed depending on the operation modes and detail design procedure of the 10kW EV fast charger converter module using proposed converter topology were described. The proposed converter and the gate driver were identified through PSpice simulation. The 60kW EV fast charger which generates output voltage ranges from 50V to 500V and maximum 150A of output currents using six parallel operated 10kW converter modules were designed and implemented. Using 60kW fast charger, the charging experiments for three types of high-capacity batteries were performed which have a different charging voltage and current. From the simulation and experimental results, it is verified that the proposed converter topology can be effectively used as main converter topology for EV fast charger.

• 센서학회지
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• 제9권4호
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• pp.288-296
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• 2000

$64{\sim}85\;{\Omega}$의 저출력저항을 갖는 박막 크로멜-알루멜 다중접합 열전변환기의 입력-출력 관계는 근사적으로 제곱법칙을 따랐지만, 전압 감응도는 공기 중 및 진공 중에서 각각 $0.34{\sim}0.67\;V/W$ 및 $1.15{\sim}1.48\;V/W$로서 매우 작았고, 공기 중에서 교류-직류 전압 변환오차는 입력이 1 V의 정현파 실효전압일 때 $40\;Hz{\sim}10\;kHz$의 주파수 범위에서 약 +340 ppm으로서 매우 크게 나타났다. 열전변환기의 큰 변환오차는 주로 저출력저항으로부터 기인된 작은 전압 감응도 및 큰 열손실 때문으로 생각되고, 따라서 작은 교류-직류 변환오차를 얻기 위한 최적화가 필요하다.

• 한국전자파학회논문지
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• 제15권6호
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• pp.608-618
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• 2004

본 논문에서는 Maas의 die 이중평형혼합기 회로를 개선, 새로운 pHEMT resistive star 이중평형혼합기 회로를 제안하였다. Star 구조로 구성되기 때문에 기존의 FET ring 혼합기 구조와 달리 별도의 IF balun이 필요로 하지 않는다. 또한 Maas의 직관적인 이중 balun설계 방법을 개선 EM simulation을 통한 이중 balun을 구성하는 방법을 제시하였다. 제안된 혼합기 회로는 CPW(Coplanar Waveguide)를 기반으로 하여 동국대 0.1 um GaAs pHEMT library를 이용 MMIC로 제작하였다. 제작된 혼합기는 크기 1.5 ${\times}$ 1.5 $\textrm{mm}^2$이며 DC bias로 성능 조정이 가능하다. 이것은 up/down converter로 사용 가능하며 V-band전역 이상의 주파수 대역폭을 갖고, 변환손실은 약 13∼18 ㏈ 정도이다.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제51권10호
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• pp.581-586
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• 2002

To improve the current waveform of diode rectifiers, we propose a new operating principle for the voltage-doubler diode rectifiers. In the conventional voltage-doubler rectifier circuit, relatively large capacitors are used to boost the output voltage, while the proposed circuit uses smaller ones and a small reactor not to boost the output voltage but improve the input current waveform. A circuit design method is shown by experimentation and confirmed simulation. The experimental results of the proposed diode rectifier satisfies the harmonic guide lines. A high input power factor of 97(%) and an efficiency of 98[%] are also obtained. The new rectifier with no controlled switches meet the harmonic guide lines, resulting in a simple, reliable and low-cost at-to dc converters in comparison with the boost-type current-improving circuits. This paper proposes a nonlinear impedance circuit composed by diodes and inductors or capacitors. This circuit needs no control circuits and switches, and the impedance value is changed by the polarity of current or voltage. And this paper presents one of these applications to improve the input current of capacitor input diode rectifiers. The rectifier using the nonlinear impedance circuit is constructed with four diodes and four capacitors in addition to the conventional rectifiers, that is, it has eight diodes and five capacitors, including a DC link capacitor. It makes harmonic components of the input current reduction and the power factor improvement. Half pulse-width modulated (HPWM) inverter was explained compared with conventional pulse width modulated(PWM) inverter. Proposed HPWM inverter eliminated dead-time by lowering switching loss and holding over-shooting.

• Journal of Electrical Engineering and Technology
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• 제13권5호
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• pp.1886-1900
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• 2018

This paper proposes a confronting feedback control structure and controllers for positive output elementary super lift Luo converters (POESLLCs) working in discontinuous conduction mode (DCM). The POESLLC offers the merits like high voltage transfer gain, good efficiency, and minimized coil current and capacitor voltage ripples. The POESLLC working in DCM holds the value of not having right half pole zero (RHPZ) in their control to output transfer function unlike continuous conduction mode (CCM). Also the DCM bestows superlative dynamic response, eliminates the reverse recovery troubles of diode and retains the stability. The proposed control structure involves two controllers respectively to control the voltage (outer) loop and the current (inner) loop to confront the time-varying ON/OFF characteristics of variable structured systems (VSSs) like POESLLC. This study involves two different combination of feedback controllers viz. the proportional integral controller (PIC) plus sliding mode controller (SMC) and the fuzzy logic controller (FLC) plus SMC. The state space averaging modeling of POESLLC in DCM is reviewed first, then design of PIC, FLC and SMC are detailed. The performance of developed controller combinations is studied at different working states of the POESLLC system by MATLAB-Simulink implementation. Further the experimental corroboration is done through implementation of the developed controllers in PIC 16F877A processor. The prototype uses IRF250 MOSFET, IR2110 driver and UF5408 diodes. The results reassured the proficiency of designed FLC plus SMC combination over its counterpart PIC plus SMC.

• Journal of Power Electronics
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• 제19권5호
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• pp.1108-1121
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• 2019

The non-inverting buck-boost converter (NIBB) is a step-up and step-down DC-DC converter suitable for wide-input-voltage-range applications. However, when the input voltage is close to the output voltage, the NIBB needs to operate in the buck-boost mode, causing a significant efficiency reduction since all four switches operates in the PWM mode. Considering both the current stress limitation and the efficiency optimization, a novel design methodology for the optimal phase-shift modulation of a NIBB in the buck-boost mode is proposed in this paper. Since the four switches in the NIBB form two bridges, the shifted phase between the two bridges can serve as an extra degree of freedom for performance optimization. With general phase-shift modulation, the analytic current expressions for every duty ratio, shifted phase and input voltage are derived. Then with the two key factors in the NIBB, the converter efficiency and the switch current stress, taken into account, an objective function with constraints is derived. By optimizing the derived objective function over the full input voltage range, an offline design methodology for the optimal modulation scheme is proposed for efficiency optimization on the premise of current stress limitation. Finally, the designed optimal modulation scheme is implemented on a DSPs and the design methodology is verified with experimental results on a 300V-1.5kW NIBB prototype.

• Journal of Power Electronics
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• 제19권4호
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• pp.846-857
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• 2019

Voltage step-down converters are very popular in distributed power systems, voltage regular modules, electric vehicles, etc. However, a high step-down voltage ratio is required in many applications to prevent the traditional buck converter from operating at extreme duty cycles. In this paper, a series capacitor interleaved buck converter with a soft switching technique is proposed. The DC voltage ratio of the proposed converter is half that of the traditional buck converter and the voltage stress across the one main switch and the diodes is reduced. Moreover, by paralleling the series connected auxiliary switch and the auxiliary inductor with the main inductor, zero voltage transition (ZVT) of the main switches can be obtained without increasing the voltage or current stress of the main power switches. In addition, zero current turned-on and zero current switching (ZCS) of the auxiliary switches can be achieved. Furthermore, owing to the presence of the auxiliary inductor, the turned-off rate of the output diodes can be limited and the reverse-recovery switching losses of the diodes can be reduced. Thus, the efficiency of the proposed converter can be improved. The DC voltage gain ratio, soft switching conditions and a design guideline for the critical parameters are given in this paper. A loss analysis of the proposed converter is shown to demonstrate its advantages over traditional converter topologies. Finally, experimental results obtained from a 100V/10V prototype are presented to verify the analysis of the proposed converter.