• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.18-24
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• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.

• Journal of International Area Studies (JIAS)
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• v.22 no.1
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• pp.161-202
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• 2018

The purpose of this study is to analyze the ex-post evaluation reports of KOICA's grant aid project in terms of criteria, methods, and contents. To this end, we will examine the evaluation history and process with particular reference to EDCF and KOICA. Our key research questions are: 1) How are the evaluation standards of the OECD DAC reflected in the KOICA ex-post evaluation reports? 2) Whether did Korea's practices of development evaluation change after its entry into the OECD DAC. The paper attempted an content analysis on the key words used in findings and recommendation section of the reports since 1998 that ara available on the website of KOICA. The main results can be summarized as follows. First, the frequency of OECD DAC criteria(relevance, efficiency, effectiveness, impact, sustainability) and the use of quantitative methods have been increasing after joining the OECD DAC. Second, in the ex-post evaluation reports issued after 2010, the reference indices including the Project Design Matrix (PDM), baseline data, and performance have increased exponentially.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4B
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• pp.288-297
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• 2003

The fast retransmit and fast recovery algorithm of TCP Reno, when multiple packets in the same window are lost, cannot recover them without RTO (Retransmission Timeout). TCP New-Reno can recover multiple lost packets by extending fast recovery using partial acknowledgement. If the retransmitted packet is lost again during fast recovery, however, RTO cannot be avoided. In this paper, we propose an algorithm called "Duplicate Acknowledgement Counting(DAC)" to alleviate this problem. DAC can detect the retransmitted packet loss by counting duplicate ACKs. Conditions that a lost packet can be recovered by loss recovery of TCP Reno, TCP New-Reno and TCP New-Reno using DAC are derived by modeling loss recovery behavior of each TCP. We calculate the loss recovery probability for random packet loss probability numerically, and show that DAC can improve loss recovery behavior of TCP New-Reno.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.683-686
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• 1998

This paper introduces a sigma-delta DAC with a fully-differential current-mode semidigital IFIR postfilter. A proposed fully-differential postfilter exhibits not only an improved SNR(signal-to-noise ratio) but also a reduced opwer dissipation.

• Journal of the Korean Society for Nondestructive Testing
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• v.23 no.6
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• pp.605-615
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• 2003

In practice, it is common to manufacture reference blocks containing simple reflectors to obtain distance-amplitude correction (DAC) curves. However, the construction or DAC curves in this manner requires the use of a large number of specimens with appropriate curvatures and reference reflectors located at various depths. Therefore, less costly and quantitative procedures are strongly needed. To address such a need, in this study, we have developed model-based transfer curves to relate a DAC curve obtained in a particular reference configuration with that for a completely different configuration. An example of transferring DAC curves, using the proposed transfer curves, is given.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2065-2069
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• 2014

The DAC-7512E is a 12-bit digital to analog converter that is low power and a single package with internal buffers. The DAC-7512E takes up minimal PCB area for applications of space power electronics design. The spacecraft mass is a crucial point considering spacecraft launch into space. Therefore, we have performed a TID test for the DAC-7512E 12-bit serial input digital to analog converter to reduce the spacecraft mass by using a low-level Gamma-ray irradiator with $Co^{60}$ gamma-ray sources. The irradiation with $Co^{60}$ gamma-rays was carried out at doses from 0 krad to 100 krad to check the error status of the device in terms of current, voltage and bit error status during conversion. The DAC-7512E 12-bit serial digital to analog converter should work properly from 0 krad to 30 krad without any error.

• International Journal of Internet, Broadcasting and Communication
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• v.5 no.2
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• pp.11-14
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• 2013

This paper describes the sigma-delta ADC/DAC digital block with two channels. The ADC block has comb filter and three half band filters. And the DAC block has 5th Cascaded-of-Integrators Feedback DSM. The ADC and DAC support I2S, RJ, LJ and selectable input data modes of 24bit, 20bit, and 16bit. It is fabricated with 0.35um Hynix standard CMOS cell library. The chip size is 3700*3700um. It has been verified using NC Verilog Simulator and Matlab Tool.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1168-1170
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• 2005

This paper deals with the conductor bar design to improve starting stability of line-start synchronous reluctance motor(LSRM). As design variables, the number and the shape of conductor bars of rotor are chosen. The starting characteristics are calculated by finite element method(FEM) and the conductor bars are designed to improve the starting torque according to initial starting rotor position. Finally, the starting characteristic of the designed model are compared with that of the initial model.

• Proceedings of the Korea Information Processing Society Conference
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• 2018.05a
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• pp.484-485
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• 2018

DAC 는 디지털-아날로그 변환 회로는 디지털 전기 신호를 아날로그 전기 신호로 변환하는 전자 회로이다. 특히 최근 음성 신호는 그 효율성 및 경제성 때문에 디지털 데이터 형태로 저장/전송되고 있어 DAC 는 음성 관련 사업에서 필수적으로 쓰이고 있다. 본 논문은 음성 신호의 디지털-아날로그 변환 시 DAC 의 성능에 대한 분석 및 시험 결과를 소개한다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.50-59
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• 1998

This paper describes a 3.3V 8bit CMOS digital to analog converter (DAC) with two state current cell metrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allow the designed DAC to reduce hot only a complexity of decoding logics, but also a number of wider swing cascode curent mirros. The designed DAC with an active chip area of 0.8 mm$_{2}$ is fabricated by a 0.8 .mu.m CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are6ns, 15ns, and a less than .+-.0.8/.+-.0.75 LB, respectively. The designed DAC is fully operational for the power supply down to 2.0V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3V is measured to be 34.5mW.