• KDI Journal of Economic Policy
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• v.33 no.4
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• pp.49-83
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• 2011

Ever since the UN Summit agreed on the MDGs in 2000, OECD/DAC member countries have taken poverty reduction as the main goal of their aid. To achieve this goal, all donors and recipient countries agreed on the Paris Declaration on Aid Effectiveness in 2005. To monitor and evaluate the progress in the targets of the Declaration, all donors and recipients got together periodically, and the 2011 conference was held in Busan, Korea. As part of this effort, this paper aims to assess the extent to which DAC donors have allocated their aid to achieve the MDGs during the latest millennium era: 2005-2009. In addition, to compare the aid allocation performance between DAC members and non-DAC emerging donors, this paper also assesses the aid allocation performance of Korea (KOICA) for the same period. The analysis of this paper shows evidence contrary to the recent literature findings that donors tended to select, as their aid recipients, those countries that warranted more aid on account of their acute development needs, and good policies and institutions. The difference between the recent literature and this paper is attributed to the different sample periods and/or the weaknesses of the estimation models and methods adopted in the literature. This paper shows why a different estimation method is adopted and why its estimation results are more reliable and convincing. This paper also shows the difference between DAC and non-DAC donors in the aid allocation performance by analyzing aid allocations by the representative aid agency of Korea (KOICA), and recommends some policy measures to be taken by both DAC and non-DAC donors.

• 전자공학회논문지 IE
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• v.43 no.3
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• pp.6-12
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• 2006

This paper described an 8bit, 100Msample/s CMOS D/A converter using a glitch-time minimization technique for the high-speed sampling rate of 100MHz level. The proposed DAC was implemented in $0.35{\mu}m$ Hynix CMOS technology and adopts a current mode architecture to optimize sampling rate, resolution, chip area. The DAC linear characteristics was similar to the proposed specification and the prototype error between DNL and INL is less than $\pm$0.09LSB respectively. Also, the manufactured DAC chip was analyzed the cause of error operation and proposed the field considerations for chip test.

• Transactions of the Korean Society of Pressure Vessels and Piping
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• v.11 no.2
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• pp.20-24
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• 2015

During refueling Outage, In-service inspections(ISIs) for the Nuclear Power Plant components are mandatory requirement in accordance with ASME Code Sec. XI. Especially, in current ultrasonic testing is one of the most important NDT techniques that are used for volumetric examination methods for nuclear power plant components, and accurate sizing of flaw indication by UT is essential to assure the integrity of the components. However, ASME code specifies minimum requirement for vessel examination procedure, and so far many different flaw sizing approaches have been tried to apply. Through the Round Robin Test(RRT), the accuracy of ultrasonic flaw sizing using DAC techniques was measured with the mock-ups simulating typical pressure vessel welds. These mock-ups contain artificially introduced flaws of known size and location. This paper shows experimental comparison data on the accuracy of techniques using such as 6dB drop, 50%DAC, 20%DAC and 20%DAC with beam spread correction, and also shows that diverse DAC techniques can be effectively applied to the assessment of the flaw sizing for pressure vessel welds in the stage of welding and fabrication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.39-45
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• 2011

This paper proposes a low power current-steering 10-bit DAC selecting clock enable signal. The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in wihich the data will not be changed. The proposed DAC was implemented using a 0.13${\mu}m$ CMOS process with $V_{DD}=1.2V$. Its core area is 0.21$mm^2$. It consumes 4.46mW at 1MHz signal frequency and 200MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25MHz and 10MHz signal frequencies, respectively. The measured SFDRs are 72.8dB and 56.1dB at 1MHz and 50MHz signal frequencies, respectively.

• Journal of Digital Convergence
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• v.17 no.12
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• pp.35-44
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• 2019

This study analyzes the relationship between OECD DAC aid and recipients' corruption based on the good governance discussion. The study applies a fixed-effect model and PCSE model with a dataset of 43 African countries' corruption perception index, World Bank data, Polity IV, and OECD DAC aid statistics between 2000 and 2014. A statistical analysis confirmed that OECD DAC aid has a negative impact on corruption in African countries. DAC's aid affects negatively to corruption in African countries, especially in countries where democracy has matured. This research suggests that a more comprehensive follow-up study of the OECD DAC's good governance-oriented aid. Simultaneously, the general democratic effect on the recipients' institutions could not be applied in African countries, when considering regional peculiarities.

• Transactions on Electrical and Electronic Materials
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• v.10 no.2
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• pp.44-48
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• 2009

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

• ETRI Journal
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• v.35 no.1
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• pp.158-161
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• 2013

This letter proposes a low-power current-steering digital-to-analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in which the data will not be changed. The 10-bit DAC is implemented using a $0.13-{\mu}m$ CMOS process with $V_{DD}$=1.2 V. Its area is $0.21\;mm^2$. It consumes 4.46 mW at a 1-MHz signal frequency and 200-MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25-MHz and 10-MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1-MHz and 50-MHz signal frequencies, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.270-277
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• 2012

This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

• IT SoC Magazine
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• s.19
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• pp.24-28
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• 2007

올해 44회를 맞이한 DAC(Design Automation Conference)는 6월 4일부터 8일까지 5일간 캘리포니아 샌디에고에서 개최되었다. 이번 DAC에도 샌프란시스코에서 열렸던 43회 DAC와 마찬가지로 인텔, IBM, ARM, Sun Microsystems 등 첨단 SoC/IP 설계회사와 Cadence, Synopsys 등 EDA 개발회사, 그리고 TSMC, UMC 등 유수의 파운드리회사들이 참가하였다. 전시회 참여업체는 약 250여개로 예년보다 약간 증가하였고 총 참관객수는 11,000여명으로 다소 줄어들었다. 하지만 국내 참여업체 관계자들은 참관객들의 질적인 수준이 작년 DAC보다 더 높아 제품을 홍보하고 관련 업계 사람들과 정보를 교환하기에 더없이 좋은 기회였다고 평가했다. 또한 이번 DAC 컨퍼런스는 총 10개 트랙, 53개의 세션들이 진행되었으며 약 161개의 논문이 발표되어 매우 역동적인 기술교류가 이루어졌다. 여기에서는 44th DAC의 주요 이슈와 전시회에 참여하였던 국내 SoC업체들의 제품에 대해 살펴 보고자한다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.3
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• pp.627-631
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• 2009

This paper presents a novel current steering cell matrix DAC(digital-to-analog converter) architecture to reduce decoder area. The current cell matrix of a existing architecture is selected by columns and lows thermometer code decoder of input bits. But The current cell matrix of a proposal architecture is divided 2n by the thermometer code decoder of upper input bits and are selected by the thermometer code decoder of middle and lower input bits. Because of this configuration, decoder numbers have increased. But the gate number that composed of decoder has decreased. In case of the designed 8 bit current steering cell matrix DAC, the gate number of decoder has decreased by about 55% in comparison with a existing architecture.