• Title/Summary/Keyword: D-S DAC

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Research for Thrust Distribution Method of DACS for Response to Pintle Actuating Failure (DACS 추진기관의 핀틀 구동장치 고장을 허용하는 추력 분배기법 연구)

  • Ki, Taeseok
    • Journal of the Korean Society of Propulsion Engineers
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    • v.21 no.5
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    • pp.61-70
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    • 2017
  • Robust thrust distribution method of solid DACS is researched. For the case of the system which has higher number of actuation nozzles than the degree of freedom of thrust to be controlled, the robust thrust allocation law which accommodate the abnormal operation is suggested. Assuming the situation that some nozzles are uncontrollable, the error between nozzle throat area command and response can be calculated. The error is used for realtime reshaping of weighting matrix. From the weighting effect, the nozzle which operated abnormally has low responsibility for the command then, the thrust error is reduced. The suggested algorithm is verified by the simulation of abnormal operation condition of DCS and ACS nozzle respectively.

A Frequency Synthesizer for MB-OFDM UWB with Fine Resolution VCO Tuning Scheme (고 해상도 VCO 튜닝 기법을 이용한 MB-OFDM UWB용 주파수 합성기)

  • Park, Joon-Sung;Nam, Chul;Kim, Young-Shin;Pu, Young-Gun;Hur, Jeong;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.8
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    • pp.117-124
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    • 2009
  • This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (Multi-Band OFDM) UWB (Ultra- Wideband) application using 0.13 ${\mu}m$ CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and LO Mixer architecture are also presented in this paper. A new mixed coarse tuning scheme that utilizes the MIM capacitance, the varactor arrays, and the DAC is proposed to expand the VCO tuning range. The frequency synthesizer can also provide the clock for the ADC in baseband modem. So, the PLL for the ADC in the baseband modem can be removed with this frequency synthesizer. The single PLL and two SSB-mixers consume 60 mW from a 1.2 sV supply. The VCO tuning range is 1.2 GHz. The simulated phase noise of the VCO is -112 dBc/Hz at 1 MHz offset. The die area is 2 ${\times}$ 2mm$^2$.

Recent Progress in R&D and Prospect of Divert and Attitude Control System(DACS) (궤도천이 및 자세제어 시스템의 연구개발 동향과 전망)

  • Kim, Seongsu;Huh, Hwanil
    • Journal of the Korean Society of Propulsion Engineers
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    • v.16 no.6
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    • pp.62-72
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    • 2012
  • Divert and attitude control system(DACS) plays an important role for orbit transfer and attitude control, and therefore becomes important subject for recent space vehicle and Precision Guided Missile(PGM) development. To develop DACS system, main research areas include shape combination of pintle and nozzle to maximize thrust change, and reduction of aerodynamic pintle load to minimizle pintle driving force, and development of multi-axis control algorithm. In this paper, introduction, classification, and overseas/domestic research and development program, and prospects of DACS are reviewed and summarized.

Development of a battery management system(BMS) simulator for electric vehicle(EV) cars (EV용 배터리 관리시스템(BMS) 시뮬레이터 개발)

  • Park, Chan-Hee;Kim, Sang-Jung;Hwang, Ho-Suk;Lee, Hee-Gwan
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.6
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    • pp.2484-2490
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    • 2012
  • This study reports on the development and performance verification of cell simulation boards of simulator and the embedded program for board control of the battery management system (BMS) of electric vehicle (EV) cars, which manages the next-generation automotive lithium-ion battery pack. Here, we have improved the speed of the simulator by using operational (OP) amplifier and transistors that were connected in series. In addition, using a digital analog converter (DAC) in each channel, we have improved the performance by channel-to-channel isolation (isolation) as compared to the traditional methods. Furthermore, by constructing a current-limiting protection circuit, one can be protected from disturbance and, by utilizing a precision shunt resistor for the current sensor, we have increased the precision of the current control. In order to verify the performance of the developed simulator, we have performed the experiment 10 times, with values ranging from 0.5 V to 5 V, and a voltage drop step of 0.5 V. Significance analysis of experimental data, and repeatability tests were performed, showing an average standard deviation of 0.001~0.004 V, indicating high repeatability and high statistical significance of the current method and system.

Delta Sigma Modulation of Controller Input Signal for the LED Light Driver (시그마 델타 변조에 의한 LED 드라이버의 입력 콘트롤러 설계)

  • Um, Kee-Hong
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.16 no.2
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    • pp.151-155
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    • 2016
  • In this paper, we present the LED dimming control system by using ADPCM (Adaptive Differential Pulse Code Modulation). This ADPCM apparatus accurately controls the LED current with high resolution reducing the RFI (radio frequency interference) due to the spreading out of the harmonics of current of pulses. Additionally, this makes it easier to increase the accuracy of control operation. This study introduces to make a digitally controlled circuit for controlling LED with high-energy efficient by adopting pulse current to LED. The LED current drive system we designed are two systems, the digitally-controlled unit and analog switching mode power supply unit, can be developed separately. The simulation shows the sigma delta modulation of digital to analog converter's output when the input level is 0.7. From this simulation, the output is approached to accurately 0.15% to target value with 510 pulses.

Fuzzy Logic PID controller based on FPGA

  • Tipsuwanporn, V.;Runghimmawan, T.;Krongratana, V.;Suesut, T.;Jitnaknan, P.
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1066-1070
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    • 2003
  • Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

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A 12 bit 750 kS/s 0.13 mW Dual-sampling SAR ADC

  • Abbasizadeh, Hamed;Lee, Dong-Soo;Yoo, Sang-Sun;Kim, Joon-Tae;Lee, Kang-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.6
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    • pp.760-770
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    • 2016
  • A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

A 2.4-GHz Low-Power Direct-Conversion Transmitter Based on Current-Mode Operation (전류 모드 동작에 기반한 2.4GHz 저전력 직접 변환 송신기)

  • Choi, Joon-Woo;Lee, Hyung-Su;Choi, Chi-Hoon;Park, Sung-Kyung;Nam, Il-Ku
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.12
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    • pp.91-96
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    • 2011
  • In this paper, a low-power direct-conversion transmitter based on current-mode operation, which satisfies the IEEE 802.15.4 standard, is proposed and implemented in a $0.13{\mu}m$ CMOS technology. The proposed transmitter consists of DACs, LPFs, variable gain I/Q up-conversion mixer, a divide-by-two circuit with LO buffer, and a drive amplifier. By combining DAC, LPF, and variable gain I/Q up-conversion mixer with a simple current mirror configuration, the transmitter's power consumption is reduced and its linearity is improved. The drive amplifier is a cascode amplifier with gain controls and the 2.4GHz I/Q differential LO signals are generated by a divide-by-two current-mode-logic (CML) circuit with an external 4.8GHz input signal. The implemented transmitter has 30dB of gain control range, 0dBm of maximum transmit output power, 33dBc of local oscillator leakage, and 40dBc of the transmit third harmonic component. The transmitter dissipates 10.2mW from a 1.2V supply and the die area of the transmitter is $1.76mm{\times}1.26mm$.

Design of wireless sensor network and its application for structural health monitoring of cable-stayed bridge

  • Lin, H.R.;Chen, C.S.;Chen, P.Y.;Tsai, F.J.;Huang, J.D.;Li, J.F.;Lin, C.T.;Wu, W.J.
    • Smart Structures and Systems
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    • v.6 no.8
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    • pp.939-951
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    • 2010
  • A low-cost wireless sensor network (WSN) solution with highly expandable super and simple nodes was developed. The super node was designed as a sensing unit as well as a receiving terminal with low energy consumption. The simple node was designed to serve as a cheaper alternative for large-scale deployment. A 12-bit ADC inputs and DAC outputs were reserved for sensor boards to ease the sensing integration. Vibration and thermal field tests of the Chi-Lu Bridge were conducted to evaluate the WSN's performance. Integral acceleration, temperature and tilt sensing modules were constructed to simplify the task of long-term environmental monitoring on this bridge, while a star topology was used to avoid collisions and reduce power consumption. We showed that, given sufficient power and additional power amplifier, the WSN can successfully be active for more than 7 days and satisfy the half bridge 120-meter transmission requirement. The time and frequency responses of cables shocked by external force and temperature variations around cables in one day were recorded and analyzed. Finally, guidelines on power characterization of the WSN platform and selection of acceleration sensors for structural health monitoring applications were given.

Database Security System supporting Access Control for Various Sizes of Data Groups (다양한 크기의 데이터 그룹에 대한 접근 제어를 지원하는 데이터베이스 보안 시스템)

  • Jeong, Min-A;Kim, Jung-Ja;Won, Yong-Gwan;Bae, Suk-Chan
    • The KIPS Transactions:PartD
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    • v.10D no.7
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    • pp.1149-1154
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    • 2003
  • Due to various requirements for the user access control to large databases in the hospitals and the banks, database security has been emphasized. There are many security models for database systems using wide variety of policy-based access control methods. However, they are not functionally enough to meet the requirements for the complicated and various types of access control. In this paper, we propose a database security system that can individually control user access to data groups of various sites and is suitable for the situation where the user's access privilege to arbitrary data is changed frequently. Data group(s) in different sixes d is defined by the table name(s), attribute(s) and/or record key(s), and the access privilege is defined by security levels, roles and polices. The proposed system operates in two phases. The first phase is composed of a modified MAC (Mandatory Access Control) model and RBAC (Role-Based Access Control) model. A user can access any data that has lower or equal security levels, and that is accessible by the roles to which the user is assigned. All types of access mode are controlled in this phase. In the second phase, a modified DAC(Discretionary Access Control) model is applied to re-control the 'read' mode by filtering out the non-accessible data from the result obtained at the first phase. For this purpose, we also defined the user group s that can be characterized by security levels, roles or any partition of users. The policies represented in the form of Block(s, d, r) were also defined and used to control access to any data or data group(s) that is not permitted in 'read ' mode. With this proposed security system, more complicated 'read' access to various data sizes for individual users can be flexibly controlled, while other access mode can be controlled as usual. An implementation example for a database system that manages specimen and clinical information is presented.