• Journal of Power Electronics
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• v.14 no.1
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• pp.40-47
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• 2014

An average current mode control scheme that consistently offers good dynamic performance for LLC series resonant DC-to-DC converters irrespective of the changes in the operational conditions is presented in this paper. The proposed control scheme employs current feedback from the resonant tank circuit through an integrator-type compensation amplifier to improve the dynamic performance and enhance the noise immunity and reliability of the feedback controller. Design guidelines are provided for both current feedback and voltage feedback compensation. The performance of the new control scheme is demonstrated through an experimental 150 W converter operating with 340 V to 390 V input voltage to provide a 24 V output voltage.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.4
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• pp.364-372
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• 2016

In this paper, a voltage controller for the seamless transition of a grid-connected inverter for ESS is proposed. The single-phase inverter is operated as a current controller when the grid is connected and as a voltage controller in the stand-alone mode when the grid is disconnected. Generally, in the case of grid recovery, the overcurrent may flow into the system because of the mismatch phase between the inverter output and grid voltages. The proposed controller resolves the overcurrent problem through phase delay problems with initial value feed-forward control of the integrator when the grid voltage is restored. The effects of the control method are simulated through PSIM, and the usefulness of the control method is verified through experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.3
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• pp.231-239
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• 1999

An improved version of current-regulated delta modulator (CRDM) is investigated for the output cunent control of v voltage-source inverters that have transformer-coupled series resonant load and are operated at the resonant frequency. Conventional CRDM has not only CUlTent offset problem but also transformer flux saturation problem when i it is applied to induction heating systems that have transformel-coupled loads. To cope with these problems, the effect of flux saturation is analysed, and simple method to av이d the problem is proposed. And integral type of CRDM is a adopted to remove the cunent offset. The boundaries of integrator gain for stable operation is calculated using the c concept of sliding mode controL The validity of proposed strategy is vel퍼ed through simulations and prototype e experiments.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.4
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• pp.28-34
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• 2000

In this paper, a continuous-time filter for low voltage and high frequency applications using fully-balanced current integrators is presented. As the balanced structure of integrator circuits, the designed filter has improved noise characteristics and wide dynamic range since even-order harmonics are cancelled and the input signal range is doubled. Using complementary current mirrors, bias circuits are simplified and the cutoff frequency of filters can be controlled easily by a single DC bias current. As a design example, the 3rd-order lowpass Butterworth filter with a leapfrog realization is designed. The designed fully-balanced current-mode filter is simulated and examined by SPICE using 0.65${\mu}{\textrm}{m}$ CMOS n-well process parameters. The simulation results show 50MHz cutoff frequency, 69㏈ dynamic range with 1% total harmonic distortion(THD), and 4㎽ power dissipation with a 3V supply voltage.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.201-210
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• 2018

This paper proposes a new start-up method for a load commutated inverter (LCI) in a large synchronous gas-turbine generator. The initial rotor position for start-up torque is detected by the proposed initial angle detector, which consists of an integrator and a phase-locked loop. The initial rotor position is accurately detected within 150ms, and the angle difference between the real position and the detected position is less than 1%. The LCI system operates in two modes (forced commutation mode and natural commutation mode) according to operating speed range. The proposed controllers include a forced commutation controller for the low-speed range, a PI speed controller and a PI current controller, where the forced commutation controller is connected to the current controller in parallel. The current controller is modeled by Matlab/Simulink, where a six-pulse delay of the thyristor and a processing delay are considered by using a zero-order hold. The performance of the proposed start-up method is evaluated in Matlab/Psim at standstill and at low speed. To verify the feasibility of the method, a 5kVA LCI system prototype is implemented, and the proposed initial angle detector and the system performance are confirmed by experimental results from standstill to 900rpm.

• Proceedings of the KIEE Conference
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• 2000.07e
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• pp.149-151
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• 2000

본 논문에서는 완전균형 상보형 적분기에서 그 이득과 단위이득 주파수 특성을 향상시킬 수 있는 high-swing cascode 구조를 이용한 새로운 적분기를 설계하였다. 설계된 high-swing cascode 적분기는 $0.25{\mu}m$ n-well CMOS 공정 파라미터를 이용하여 HSPICE 시뮬레이션 하였으면, 그 결과 제안된 회로는 2V 공급전압에서 전력소모는 1.04mW이고 차단주파수는 100MHz를 갖으며 이득은 51dB로서 이 적분기를 이용한 능동필터 설계시 요구조건인 40dB 이상의 이득 값을 만족한다.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.3
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• pp.184-196
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.