• 제목/요약/키워드: Current-Sensing scheme

검색결과 83건 처리시간 0.025초

MOSFET을 이용한 전동기 구동을 위한 저가격형 전류검출법 (A Low-Cost Current-Sensing Scheme for MOSFET Motor Drives)

  • 장성동;정재호;박종규;이균정;신휘범
    • 전력전자학회논문지
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    • 제8권1호
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    • pp.40-47
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    • 2003
  • A low-cost current-sensing scheme for the motor drives with MOSFET is described. Many motor drives usually employ the common current sensors to measure current for the purpose of control or protection. These current sensors, however, significantly burden the power circuit with the size and cost. The proposed current-sensing scheme utilizes information concerning MOSFET's On-voltage and On-resistance. An analogue circuit detecting On-voltage can overcome the above disadvantages because the circuit is small and is made at a low cost, and the fuzzy inference for On-resistance is also simply designed based on MOSFET's characteristics. The validity of this scheme will be experimentally verified by adopting the current control of a battery car.

온칩 DC-DC 변환기를 위한 전류 비교 방식의 센서 (A Sensing Scheme Utilizing Current-Mode Comparison for On-Chip DC-DC Converter)

  • 김형일;송하선;김범수;김대정
    • 대한전자공학회논문지SD
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    • 제44권4호
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    • pp.86-90
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    • 2007
  • 본 논문에서는 DC-DC 변환기에서 효율적으로 sensing 할 수 있는 센서 scheme을 제안하였다. DC-DC 변환기의 최종 출력전압을 되먹임하여 센서의 입력단에서 전류로 변환되며, 센서에 내장된 기준전류와의 전류비교를 통하여 목표전압에 도달했는지의 여부를 감지한다. 이때의 감지동작은 전류 push-pull 동작을 통해 전류 비교 방식을 수행한다. 센서에 내장된 기준전류도 고정된 기준전압을 변환함으로써 구현된다. 본 scheme의 특징은 전압을 전류로 변환하는 데 있어서의 파라미터가 코어 트랜지스터의 (W/L)의 비로써 결정되므로 비교적 정밀하고 기존의 전압 모드 방식과 비교했을 때, 전력소모 측면이나 칩 사이즈측면에서 효율적으로 구현되는 데에 있다. 본 논문에서는 입력 배터리 공급전압 2.2V${\sim}$3.6V에 대해 5V를 출력하는 DC-DC 변환기에 제안하는 센서를 적용하여 0.35um CMOS 공정으로써 구현하고 그 유용성을 확인하였다.

Widely Tunable Adaptive Resolution-controlled Read-sensing Reference Current Generation for Reliable PRAM Data Read at Scaled Technologies

  • Park, Mu-hui;Kong, Bai-Sun
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권3호
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    • pp.363-369
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    • 2017
  • Phase-change random access memory (PRAM) has been emerged as a potential memory due to its excellent scalability, non-volatility, and random accessibility. But, as the cell current is reducing due to cell size scaling, the read-sensing window margin is also decreasing due to increased variation of cell performance distribution, resulting in a substantial loss of yield. To cope with this problem, a novel adaptive read-sensing reference current generation scheme is proposed, whose trimming range and resolution are adaptively controlled depending on process conditions. Performance evaluation in a 58-nm CMOS process indicated that the proposed read-sensing reference current scheme allowed the integral nonlinearity (INL) to be improved from 10.3 LSB to 2.14 LSB (79% reduction), and the differential nonlinearity (DNL) from 2.29 LSB to 0.94 LSB (59% reduction).

Analysis of the Charge Controlled Inductor Current Sensing Peak-Power-Tracking Solar Array Regulator

  • Lee, K.S.;Cho, Y.J.;Cho, B.H.
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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    • pp.982-986
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    • 1998
  • The peak-power-tracking solar array regulator sensing the inductor current is proposed. Since it uses the inductor current as the solar array output power information, the PPT control scheme can be greatly simplified. The charge controlled two-loop scheme is presented to improve the dynamics due to the inductor current sensing. The comparison between the single-voltage loop controlled system and the two-loop controlled system employing the charge control is presented. This paper also contains the simulation results of that comparison.

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Giga Bit급 저전력 synchronous DRAM 구조에 대한 연구 (A study on the low power architecture of multi-giga bit synchronous DRAM's)

  • 유회준;이정우
    • 전자공학회논문지C
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    • 제34C권11호
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    • pp.1-11
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    • 1997
  • The transient current components of the dRAM are analyzed and the sensing current, data path operation current and DC leakage current are revealed to be the major curretn components. It is expected that the supply voltage of less than 1.5V with low VT MOS witll be used in multi-giga bit dRAM. A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme. The sensing current can be reduced by adopting 8 bit prefetch scheme with 1.2V VDD. Although the total cycle time for the sequential 8 bit read is the same as that of the 3.3V conventional DRAM, the sensing current is loered to 0.7mA or less than 2.3% of the current of 3.3V conventional DRAM. 4 stage pipeline scheme is used to rduce the power consumption in the 4 giga bit DRAM data path of which length and RC delay amount to 3 cm and 23.3ns, respectively. A simple wave pipeline scheme is used in the data path where 4 sequential data pulses of 5 ns width are concurrently transferred. With the reduction of the supply voltage from 3.3V to 1.2V, the operation current is lowered from 22mA to 2.5mA while the operation speed is enhanced more than 4 times with 6 ns cycle time.

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MRAM을 위한 새로운 데이터 감지 기법과 writing 기법 (A New Sensing and Writing Scheme for MRAM)

  • 고주현;조충현;김대정;민경식;김동명
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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    • pp.815-818
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    • 2003
  • New sensing and writing schemes for a magneto-resistive random access memory (MRAM) with a twin cell structure are proposed. In order to enhance the cell reliability, a scheme of the low voltage precharge is employed to keep the magneto resistance (MR) ratio constant. Moreover, a common gate amplifier is utilized to provide sufficient voltage signal to the bit line sense amplifiers under the small MR ratio structures. To enhance the writing reliability, a current mode technique with tri-state current drivers is adopted. During write operations, the bit and /bit lines are connected. And 'HIGH' or 'LOW' data is determined in terms of the current direction flowing through the MTJ cell. With the viewpoint of the improved reliability of the cell behavior and sensing margin, HSPICE simulations proved the validity of the proposed schemes.

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온칩 DC-DC 변환기를 위한 전류 비교 방식의 센서 (A Sensing Scheme Utilizing Current-Mode Comparison for On-Chip DC-DC Converter)

  • 김형일;송하선;김범수;김대정
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.529-530
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    • 2006
  • An efficient sensing scheme adoptable in DC-DC converter is described. The output voltage of the whole DC-DC converter is fed back to the input voltage of the sensor. The comparison in the sensor is accomplished by a current push-pull action. With a fixed reference, the comparator can be embodied based on (W/L) ratios. The current-mode scheme benefits the system better than a conventional voltage-mode one in terms of small area, low power consumption.

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Modulated Carrier Control for Interleaved Continuous Conduction Mode(CCM) Boost Power Factor Correction Converter

  • Kim, Hye-jin;Choi, Kyu-sik;Cho, B.H.;Choi, Hang-seok
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2012년도 전력전자학술대회 논문집
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    • pp.195-196
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    • 2012
  • In recent years, in an effort to improve the efficiency and the power density of the front-end power factor correction(PFC), the interleaving of multiple converter is employed. The conventional interleaved continuous conduction mode(CCM) boost PFC converter requires input and output voltage sensing and three current sensing to obtain current balancing between modules. In this paper, the interleaved CCM PFC converter based on modulated carrier control is proposed. With the proposed method, two phase interleaved PFC can be realized simply without line voltage sensing resistor and can achieve current balancing without additional current sensing resistor on common return path. The simulation studies are carried out to verify the effectiveness of the proposed control scheme.

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전류 방식 MRAM의 데이터 감지 기법 (Sensing scheme of current-mode MRAM)

  • 김범수;조충현;황원석;고주현;김동명;민경식;김대정
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.419-422
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    • 2004
  • A sensing scheme for current-mode magneto-resistance random access memory (MRAM) with a 1T1MTJ cell structure is proposed. Magnetic tunnel junction (MTJ) resistance, which is HIGH or LOW, is converted to different cell currents during READ operation. The cell current is then amplified to be evaluated by the reference cell current. In this scheme, conventional bit line sense amplifiers are not required and the operation is less sensitive to voltage noise than that of voltage-mode circuit is. It has been confirmed with HSPICE simulations using a 0.35-${\mu}m$ 2-poly 4-metal CMOS technology.

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Research on Multiple-image Encryption Scheme Based on Fourier Transform and Ghost Imaging Algorithm

  • Zhang, Leihong;Yuan, Xiao;Zhang, Dawei;Chen, Jian
    • Current Optics and Photonics
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    • 제2권4호
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    • pp.315-323
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    • 2018
  • A new multiple-image encryption scheme that is based on a compressive ghost imaging concept along with a Fourier transform sampling principle has been proposed. This further improves the security of the scheme. The scheme adopts a Fourier transform to sample the original multiple-image information respectively, utilizing the centrosymmetric conjugation property of the spatial spectrum of the images to obtain each Fourier coefficient in the most abundant spatial frequency band. Based on this sampling principle, the multiple images to be encrypted are grouped into a combined image, and then the compressive ghost imaging algorithm is used to improve the security, which reduces the amount of information transmission and improves the information transmission rate. Due to the presence of the compressive sensing algorithm, the scheme improves the accuracy of image reconstruction.