• Journal of Power Electronics
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• v.13 no.3
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• pp.349-361
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• 2013

As a result of the advantages such as high efficiency, continuous current and high stability margin, push-pull converter with continuous current (PPCWCC) is competitive for battery discharge regulator (BDR) which plays an important role in power conditioning unit (PCU). Leakage inductance yields current spike in low-ripple current of PPCWCCs. The operating modes are added due to leakage inductance. Therefore the steady state performance is affected, which is embodied in the spike of low-ripple current. PPCWCCs which are suitable for BDR can be separated into three types by current spike characteristics. Three representative topologies IIs1, IIcb2 and Is3 are analyzed in order to investigate the factors on the magnitude and duration of spike. Equivalent current sampling method (ECSM) which eliminates the sampling time delay and achieves excellent dynamic performance is adopted to prevent the spike disturbance on current sampling. However, ECSM reduces the sampling accuracy and telemetry accuracy due to neglecting the spike. In this paper, ECSM used in PPCWCCs is summarized. The current sampling error is analyzed in quality and quantity, which provides the foundation for offsetting and enhancing the telemetry accuracy. Finally, current sampling error rate of three topologies is compared by experiment results, which verify the theoretical analysis.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.9
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• pp.517-522
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• 1999

This paper addresses the issue of current sampling in a high performance AC drive system fed by a discontinuous PWM inverter. The effect of the sampling error due to the measurement delay produced by an input stage low pass filter and an A/D converter is described in the case of discontinuous PWM. To compensate for the sampling error, a method to estimate the delay time of the whole measurement system based on the measured current is proposed and its effectiveness is verified by experimental results. The proposed algorithm can automatically estimate the system delay introduced by the low pass filter and the A/D converter at the commissioning stage. By delaying the current sampling by the estimated value, experimental results indicate that more than 50% reduction of current ripple can be achieved.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.5
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• pp.462-473
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• 1999

This paper addresses the current measurement issue of all digital field oriented control of ac motors. The p paper focuses on the effect of low-pass filter and also on the sampling of the fundamental component of the m motor current. The low-pass filter, which suppresses the switching noise of the motor current, introduces v variable phase delay according to the current ripple frequency. It is shown that the current sampling error c consists of the fundamental component and high frL'quency ripple components. In this paper, the dependency of t this current sampling e$\pi$or on the reference voltage vector is investigated analytically and a sampling technique i is proposed to minimize the error. The work is based on the three phase symmetry pulse width modulation l inverter driving an induction machine. With this technique, the bandwidth of current regulator can be extended t to the limit given by the switching frequency of the inverter and more precise torque regulation is possible.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1035-1037
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• 2001

This paper presents an improved hys- teresis current control method for three-phase PWM power inverters using 3-level comparator. Hysteresis current controller using 3-level comparator has an advantage of constant switching frequency compared with conventional hysteresis current controller. However, this method has disadvantage that the longer sampling period, the larger current error because the switching is performed without considering current error magnitude of each phase. The proposed method improves the control performance by selecting the optimum switching pattern in which the magnitudes of current errors are considered introducing space vector concept. Simulation results using Matlab/Simulink show that the proposed control method reduces current error keeping the merit of previous hysteresis current control method.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1084-1087
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• 2002

This paper presents an improved fuzzy logic-based adaptive PWM technique. A fuzzy logic- based adaptive PWM technique determines the optimal output voltage vector which takes into account both direction of back-emf and direction of current error vector. This technique has a simple structure and a good level of stability, but it has disadvantages. The longer sampling period, the larger current error. Because there is no considerations of the current error magnitude of each phases. The proposed method improves the control performance by selecting the optimum switching pattern in which the magnitudes of current errors are considered introducing space vector concept. Simulation results using Matlab/Simulink show that the proposed control method reduces current error keeping the merit of previous one.

• Communications for Statistical Applications and Methods
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• v.19 no.3
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• pp.315-331
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• 2012

In this research, we estimated the number of hits per song and its sampling error from 11 (areas including Gangnam) based on log data compiling the number of hits collected from offline karaoke players in March 2011. Then, we calculated the monetary equivalent of the sampling error under the current system that distribute royalties from the karaoke players to copyright holders(song writers and arrangers) according to the estimated hits. Because of the small sample size, the estimated number of hits had a very large sampling error. This research proposes a more reasonable sample design to estimate the usage of copyrighted music works for a fair distribution of royalties by reducing sampling error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1325-1331
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• 1996

In this paper, a new current-memory circuit is proposed that reduces the clock feedthrough(CFT) error voltage causing total harmonic distortion(THD) increment in switched-current(SI) systems. Using PMOS transistor in CMOS complementary, the proposed one reduces output distortion current due to the CFT errorvoltage. A proposed current-memory is designed using a 1.2.mu.m CMOS process anda 1MHz sinusoidal signal having a 68.mu.A amplitude current is applied as input (sampling frequency:20MHz). It hasbeen shown from the simulation that the output distortion current effected by the CFT error voltage is reduced by approximately 10 times the error voltage of conventional one, THD is -57dB in case ofappling 1kHz frequency input signalwith 0.5 peak signal-to-bias current ratio.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.399-402
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• 1999

The single sensor technique reconstructing phase currents from the dc-link current without phase current sensors in proposed. When the duration of active vector is too short for the snubber current to reduce, the dc-link current including the snubber current gives large detection error. The solution is presented by analyzing the snubber current and modifying the switching sequences. This scheme is simple, requires only one sampling a period and has good results for detecting the phase currents.

• Journal of Power Electronics
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• v.11 no.1
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• pp.64-73
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• 2011

The stability of PWM rectifiers with a deadbeat current controller is seriously influenced by computation time delays and low-pass filters inserted into the current-sampling circuit. Predictive current control is often adopted to solve this problem. However, grid current predictive precision is affected by many factors such as grid voltage estimated errors, plant model mismatches, dead time and so on. In addition, the predictive current error aggravates the grid current distortion. To improve the grid current predictive precision, an improved deadbeat current controller with a repetitive-control-based observer to predict the grid current is proposed in this paper. The design principle of the proposed observer is given and its stability is discussed. The predictive performance of the observer is also analyzed in the frequency domain. It is shown that the grid predictive error can be decreased with the proposed method in the related bode diagrams. Experimental results show that the proposed method can minimize the current predictive error, improve the current loop robustness and reduce the grid current THD of PWM rectifiers.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1241-1246
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• 2005

This paper described an 8bit, 100Msample/s CMOS D/A converter using a glich-time minimization technique for the high-speed sampling rate of 100MHz level. The proposed DAC was implemented in 0,35um Hynix CMOS technology and adopts a current mode architecture to optimize sampling rate, resolution, chip area. The DAC linear characteristics was similar to the proposed specification the prototype error between DNL and INL is less than ${\pm}0.09LSB$ respectively. Also, fab-out chip was tested, analysed the cause of error operation, and proposed the field considerations for chip test.