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Seismic AVO Analysis, AVO Modeling, AVO Inversion for understanding the gas-hydrate structure (가스 하이드레이트 부존층의 구조파악을 위한 탄성파 AVO 분석 AVO모델링, AVO역산)

  • Kim Gun-Duk;Chung Bu-Heung
    • 한국신재생에너지학회:학술대회논문집
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    • 2005.06a
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    • pp.643-646
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    • 2005
  • The gas hydrate exploration using seismic reflection data, the detection of BSR(Bottom Simulating Reflector) on the seismic section is the most important work flow because the BSR have been interpreted as being formed at the base of a gas hydrate zone. Usually, BSR has some dominant qualitative characteristics on seismic section i.e. Wavelet phase reversal compare to sea bottom signal, Parallel layer with sea bottom, Strong amplitude, Masking phenomenon above the BSR, Cross bedding with other geological layer. Even though a BSR can be selected on seismic section with these guidance, it is not enough to conform as being true BSR. Some other available methods for verifying the BSR with reliable analysis quantitatively i.e. Interval velocity analysis, AVO(Amplitude Variation with Offset)analysis etc. Usually, AVO analysis can be divided by three main parts. The first part is AVO analysis, the second is AVO modeling and the last is AVO inversion. AVO analysis is unique method for detecting the free gas zone on seismic section directly. Therefore it can be a kind of useful analysis method for discriminating true BSR, which might arise from an Possion ratio contrast between high velocity layer, partially hydrated sediment and low velocity layer, water saturated gas sediment. During the AVO interpretation, as the AVO response can be changed depend upon the water saturation ratio, it is confused to discriminate the AVO response of gas layer from dry layer. In that case, the AVO modeling is necessary to generate synthetic seismogram comparing with real data. It can be available to make conclusions from correspondence or lack of correspondence between the two seismograms. AVO inversion process is the method for driving a geological model by iterative operation that the result ing synthetic seismogram matches to real data seismogram wi thin some tolerance level. AVO inversion is a topic of current research and for now there is no general consensus on how the process should be done or even whether is valid for standard seismic data. Unfortunately, there are no well log data acquired from gas hydrate exploration area in Korea. Instead of that data, well log data and seismic data acquired from gas sand area located nearby the gas hydrate exploration area is used to AVO analysis, As the results of AVO modeling, type III AVO anomaly confirmed on the gas sand layer. The Castagna's equation constant value for estimating the S-wave velocity are evaluated as A=0.86190, B=-3845.14431 respectively and water saturation ratio is $50\%$. To calculate the reflection coefficient of synthetic seismogram, the Zoeppritz equation is used. For AVO inversion process, the dataset provided by Hampson-Rushell CO. is used.

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An Adaptive Packet Loss Recovery Scheme for Realtime Data in Mobile Computing Environment (이동 컴퓨팅 환경에서 실시간 데이터의 적응적 손실 복구 방법)

  • Oh, Yeun-Joo;Baek, Nak-Hoon;Park, Kwang-Roh;Jung, Hae-Won;Lim, Kyung-Shik
    • Journal of KIISE:Information Networking
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    • v.28 no.3
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    • pp.389-405
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    • 2001
  • In these days, we have increasing demands on the real-time services, especially for the multimedia data transmission in both of wired and wireless environments and thus efficient and stable ways of transmitting realtime data are needs. Although RTP is widely used for internet-based realtime applications, it cannot avoid packet losses, due to the use of UDP stack and its underlying layers. In the case of mobile computing applications, the packet losses are more frequent and consecutive because of the limited bandwidth. In this paper, we first statistically analyze the characteristics of packet losses in the wired and wireless communications, based on Gilbert model, and a new packet recovery scheme for realtime data transmission is presented. To reflect the transmission characteristics of the present network environment, our scheme makes the sender to dynamically adjust the amount of redundant information, using the current packet loss characteristic parameters reported by the receiver. Additionally, we use relatively large and discontinuous offset values, which enables us to recover from both of the random and consecutive packet losses. Due to these characteristics, our scheme is suitable for the mobile computing environment where packet loss rates are relatively high and varies rapidly in a wide range. Since our scheme is based on the analytic model form statistics, it can also be used for other network environments. We have implemented the scheme with Mobile IP and RTP/RTCP protocols to experimentally verify its efficiency.

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Wavelet-based Pitch Detector for 2.4 kbps Harmonic-CELP Coder (2.4 kbps 하모닉-CELP 코더를 위한 웨이블렛 피치 검출기)

  • 방상운;이인성;권오주
    • The Journal of the Acoustical Society of Korea
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    • v.22 no.8
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    • pp.717-726
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    • 2003
  • This paper presents the methods that design the Wavelet-based pitch detector for 2,4 kbps Harmonic-CELP Coder, and that achieve the effective waveform interpolation by decision window shape of the transition region, Waveform interpolation coder operates by encoding one pitch-period-sized segment, a prototype segment, of speech for each frame, generate the smooth waveform interpolation between the prototype segments for voiced frame, But, harmonic synthesis of the prototype waveforms between previous frame and current frame occur not only waveform errors but also discontinuity at frame boundary on that case of pitch halving or doubling, In addtion, in transition region since waveform interpolation coder synthesizes the excitation waveform by using overlap-add with triangularity window, therefore, Harmonic-CELP fail to model the instantaneous increasing speech and synthesis waveform linearly increases, First of all, in order to detect the precise pitch period, we use the hybrid 1st pitch detector, and increse the precision by using 2nd ACF-pitch detector, Next, in order to modify excitation window, we detect the onset, offset of frame by GCI, As the result, pitch doubling is removed and pitch error rate is decreased 5.4% in comparison with ACF, and is decreased 2,66% in comparison with wavelet detector, MOS test improve 0.13 at transition region.

High-resolution Seismic Imaging of Shallow Geology Offshore of the Korean Peninsula: Offshore Uljin (신기 지구조운동의 해석을 위한 한반도 근해 천부지질의 고해상 탄성파 탐사: 울진 주변해역)

  • Kim, Han-Joon;Jou, Hyeong-Tae;Yoo, Hai-Soo;Kim, Kwang-Hee;You, Lee-Sun
    • Geophysics and Geophysical Exploration
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    • v.14 no.2
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    • pp.127-132
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    • 2011
  • We acquired and interpreted more than 650 km of high-resolution seismic reflection profiles in the Hupo Basin, offshore east coast of Korea at $37^{\circ}N$ in the East Sea (Japan Sea) to image shallow and basement deformation. The seismic profiles reveal that the main depocenter of the Hupo Basin in the study area is bounded by the large offset Hupo Fault on the east and an antithetic fault on the west; however, the antithetic fault is much smaller both in horizontal extension and in vertical displacement than the Hupo Fault. Sediment infill in the Hupo Basin consists of syn-rift (late Oligocene. early Miocene) and post-rift (middle Miocene.Holocene) units. The Hupo Fault and other faults newly defined in the Hupo Basin strike dominantly north and show a sense of normal displacement. Considering that the East Sea has been subjected to compression since the middle Miocene, we interpret that these normal faults were created during continental rifting in late Oligocene to early Miocene times. We suggest that the current ENE direction of maximum principal compressive stress observed in and around the Korean peninsula associated with the motion of the Amurian Plate induces the faults in the Hupo Basin to have reverse and right-lateral, strike-slip motion, when reactivated. A recent earthquake positioned on the Hupo Fault indicates that in the study area and possibly further in the eastern Korean margin, earthquakes would occur on the faults created during continental rifting in the Tertiary.

Design of a Wide-Frequency-Range, Low-Power Transceiver with Automatic Impedance-Matching Calibration for TV-White-Space Application

  • Lee, DongSoo;Lee, Juri;Park, Hyung-Gu;Choi, JinWook;Park, SangHyeon;Kim, InSeong;Pu, YoungGun;Kim, JaeYoung;Hwang, Keum Cheol;Yang, Youngoo;Seo, Munkyo;Lee, Kang-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.1
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    • pp.126-142
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    • 2016
  • This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.

Optimal Design of Permanent Magnet Thrust Bearings (영구자석형 스러스트 베어링의 최적 설계)

  • Yoo, Seong-Yeol;Kim, Woo-Yeon;Kim, Seung-Jong;Lee, Wook-Ryun;Bae, Yong-Chae;Noh, Myoung-Gyu
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.35 no.4
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    • pp.353-358
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    • 2011
  • In this paper, we describe a process for optimally designing a ring-type permanent magnet thrust bearing. The bearing consists of two sets of permanent magnet rings. One set is located inside the other set. An axial offset between the two sets creates axial force, which results in a thrust bearing function. In order to realize an optimal design of the bearing where the required load capacity of the bearing is achieved with the least magnet volume, we derived analytical design equations by adopting the equivalent current sheet (ECS) method. We considered the following two types of magnet arrays: axial arrays and Halbach arrays. These two types of arrays are optimized using the analytical design equations. The results of the optimization are verified using three dimensional (3D) finite element analyses (FEA). The results show that the Halbach array can achieve the required load capacity with less amount of permanent magnet than the axial array does. The efficacy of the ECS method is also verified by using 3D FEA. It is found that the accuracy of ECS method is more sensitive to the underlying assumptions for the Halbach array than for the axial array.

A study on the strategy of entering into the global value chain for defense SMEs (방산 중소기업의 글로벌 부품공급망 진입전략 연구)

  • Won, Jun-Ho
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.21 no.9
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    • pp.301-309
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    • 2020
  • Defense exports have overgrown in a short period, and items have been diversified with advanced high-end equipment, but exports have been stagnant due to the global economic recession and fierce competition. Weapons importers in the global market are diversified, volatility is higher, and global defense companies are also expanding their global value chain (GVC) By participating in the GVC of a global defense company, the defense SME can grow into a competitive company with specialized technology, rather than participating as a partner of a domestic system company. It is time to prepare an export promotion support plan. In this study, we selected five global companies with high value for the implementation of offset and general considerations on domestic SMEs' entry into the international parts supply chain and related cases, and investigated GVC entry requirements, the current status of cooperation partners, and the perceptions of GVC entry, through local surveys in Korea and overseas. Also, by considering the export target comprehensively, GVC stage, and the level of export competitiveness of domestic SMEs, strategies for promoting GVC participation of defense SMEs and improvements in government policies were derived and presented.

Sedimentary Facies and Architecture of a Gigantic Gravelly Submarine Channel System in a Cretaceous Foredeep Trough (the Magallanes Basin, Southern Chile)

  • Sohn, Young Kwan;Jo, Hyung Rae;Woo, Jusun;Kim, Young-Hwan G.;Choe, Moon Young
    • Ocean and Polar Research
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    • v.39 no.2
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    • pp.85-106
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    • 2017
  • The Lago Sofia conglomerate in southern Chile is a deep-marine gravelly deposit, which is hundreds of meters thick and kilometers wide and extends laterally for more than 100 km, filling the foredeep trough of the Cretaceous Magallanes Basin. For understanding the depositional processes and environments of this gigantic deep-sea conglomerate, detailed analyses on sedimentary facies, architecture and paleoflow patterns were carried out, highlighting the differences between the northern (Lago Pehoe and Lago Goic areas) and southern (Lago Sofia area) parts of the study area. The conglomerate bodies in the northern part occur as relatively thin (< 100 m thick), multiple units intervened by thick mudstone-dominated sequences. They show paleoflows toward ENE and S to SW, displaying a converging drainage pattern. In the southern part, the conglomerate bodies are vertically interconnected and form a thick (> 400 m thick) conglomerate sequence with rare intervening fine-grained deposits. Paleoflows are toward SW. The north-to-south variations are also distinct in sedimentary facies. The conglomerate bodies in the southern part are mainly composed of clast-supported conglomerate with sandy matrix, which is interpreted to be deposited from highly concentrated bedload layers under turbidity currents. Those in the northern part are dominated by matrix- to clast-supported conglomerate with muddy matrix, which is interpreted as the products of composite mass flows comprising a turbidity current, a gravelly hyperconcentrated flow and a mud-rich debris flow. All these characteristics suggest that the Lago Sofia conglomerate was formed in centripetally converging submarine channels, not in centrifugally diverging channels of submarine fans. The tributaries in the north were dominated by mass flows, probably affected by channel-bank failures or basin-marginal slope instability processes. In contrast, the trunk channel in the south was mostly filled by tractive processes, which resulted in the vertical and lateral accretion of gravel bars, deposition of gravel dunes and filling of scours and channels, similar to deposits of terrestrial gravel-bed rivers. The trunk channel developed along the axis of foredeep trough and its confinement within the trough is probably responsible for the thick, interconnected channel fills. The large-scale architecture of the trunk-channel fills shows an eastward offset stacking pattern, suggesting that the channel migrated eastwards most likely due to the uplift of the Andean Cordillera.

Analysis of Temperature Characteristics on Accelerometer using SOI Structure (SOI 구조 가속도센서의 온도 특성 해석)

  • Son, Mi-Jung;Seo, Hee-Don
    • Journal of Sensor Science and Technology
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    • v.9 no.1
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    • pp.1-8
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    • 2000
  • One of today's very critical and sensitive accurate accelerometer which can be used higher temperature than $200^{\circ}C$ and corrosive environment, is particularly demanded for automotive engine. Because silicon is a material of large temperature dependent coefficient, and the piezoresistors are isolated with p-n junctions, and its leakage current increase with temperature, the performance of the silicon accelerometer degrades especially after $150^{\circ}C$. In this paper, The temperature characteristic of a accelerometer using silicon on insulator (SOI) structure is studied theoretically, and compared with experimental results. The temperature coefficients of sensitivity and offset voltage (TCS and TCO) are related to some factors such as thermal residual stress, and are expressed numerically. Thermal stress analysis of the accelerometer has also been carried out with the finite-element method(FEM) simulation program ANSYS. TCS of this accelerometer can be reduced to control the impurity concentration of piezoresistors, and TCO is related to factors such as process variation and thermal residual stress on the piezoresistors. In real packaging, The avarage thermal residual stress in the center support structure was estimated at around $3.7{\times}10^4Nm^{-2}^{\circ}C^{-1}$ at sensing resistor. The simulated ${\gamma}_{pT}$ of the center support structure was smaller than one-tenth as compared with that of the surrounding support structure.

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A 12b 1kS/s 65uA 0.35um CMOS Algorithmic ADC for Sensor Interface in Ubiquitous Environments (유비쿼터스 환경에서의 센서 인터페이스를 위한 12비트 1kS/s 65uA 0.35um CMOS 알고리즈믹 A/D 변환기)

  • Lee, Myung-Hwan;Kim, Yong-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.3
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    • pp.69-76
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    • 2008
  • This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.