• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.2
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• pp.10-14
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• 1980

In this paper, the second harmonic distortion of the DH L.D. is analyzed using dynamic and static rate equations. In this analysis the modulation current Jm is changed by varang the iinjection current with the relation of where m stands for modulation index. It is showed that relative harmonic distortion ( ) has a peak exactly at the threshold current. It is also confirmed that this method is simople and more accurate than previously reported methods in the decision of the threshold current.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.782-785
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• 2005

This article introduces technique to reduce harmonic by using the $5^{th}$ and $7^{th}$ harmonic tune filter and line reactor in the comparison to the technique of intervening firing method at the pulse of the 6-pulse phase-controlled converter in every 1/6 period. The design of the technique introduced in this article is to reduce the harmonic distortion of the current and the voltage resulted from three-phase thyristor phase-controlled converter. The waveform obtained from the experiment was analyzed on the spectrum of the current, voltage and the total harmonic distortion. The double firing method causes zero vectors of output voltage and input current. Designing the mechanism of the converter based on the idea of Park Vector Theory, the number of harmonic distortion in the intervening firing method were compared to those in normal firing method.

• Proceedings of the KIEE Conference
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• 1997.07f
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• pp.1999-2001
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• 1997

The main two drawbacks of the Sin91e Stage PFC (SS-PFC) converters employing a DCM Boost PFC cell are relatively high voltage stress on the bulk capacitor and the input current harmonic distortion. The high voltage stress on bulk capacitor makes the SS-PFC converter impractical in a universal input application and the input current harmonic distortion lowers power factor. In this paper a selective variable frequency control that reduces the voltage stress on the bulk capacitor and the input current harmonic distortion is proposed. Computer simulation results of the proposed control method are presented.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.50 no.8
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• pp.373-378
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• 2001

This paper introduces a new online index to quantify the harmonic distortion. The proposed index based on VI product can represent the harmonic distortion of both voltage and current, and it includes the effect of interharmonic distortion. Also, the new index is suitable to online harmonic distortion evaluation since it only requires the r.m.s. (root mean square) value and fundamental frequency value of the signals. Case studies are presented to show the availability of the proposed index using the comparison with the THD (Total Harmonic Distortion).

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.5
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• pp.778-785
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• 2017

This paper presents a control method for reducing the distortion of the grid current at a grid-connected three-level neutral point clamped (NPC) inverter. The grid current is distorted from the 5th and 7th harmonic components in the stationary frame current also the 6th harmonic component in the synchronous frame current. In this paper, the 6th harmonic component on synchronous frame is controlled by using all-pass filters (APFs) and proportional integral (PI) controllers for distortion of the grid side. When transformed the 6th harmonic component is controlled, the 5th and 7th harmonic components are reduced. The validity of the proposed control method is verified by simulation and experiment results using a 25kW three-level NPC inverter.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.10
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• pp.1554-1560
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• 2012

In this paper, the even harmonic current(2nd, 4th, 6th, 8th) of the arc fault current and normal current were measured in computer load and analyzed. The BPF with GIC was developed to detection of harmonic, the exact center frequency and a high degree of sharpness could be easily obtained. The total even harmonic distortion due to series arc fault in computer load was 31.2%, this value was increased 3.9 times better than the total even harmonic distortion of normal current. The results of analysis of arc fault current RMS variation rate and Peak variation rate per half-cycle, The RMS average variation rate are as follows ; the 2nd harmonic was 0.24, the 4th harmonic was 0.15, the 6th harmonic was 0.19, the 8th harmonic was 0.25, respectively. The Peak average variation rate are as follows ; the 2nd harmonic was 0.19, the 4th harmonic was 0.12, the 6th harmonic was 0.13, the 8th harmonic was 0.15, respectively. The results of this analysis utilize data to detect of series arc fault on wiring of computer load.

• Journal of Power Electronics
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• v.19 no.4
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• pp.907-921
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• 2019

This paper presents two advanced hybrid pulse-width modulation (PWM) strategies for multilevel inverters (MLIs) that provide both common-mode voltage (CMV) elimination and current ripple reduction. The first PWM utilizes sequences that apply one switching state at the double ends of a half-carrier cycle. The second PWM combines the advantages of the former and an existing four-state PWM. Analyses of the harmonic characteristics of the two groups of switching sequences based on a general switching voltage model are carried out, and algorithms to optimize the current ripple are proposed. These methods are simple and can be implemented online for general n-level inverters. Using a three-level NPC inverter and a five-level CHB inverter, good performances in terms of the root mean square current ripple are obtained with the proposed PWM schemes as indicated through improved harmonic distortion factors when compared to existing schemes in almost the entire region of the modulation index. This also leads to a significant reduction in the current total harmonic distortion. Simulation and experimental results are provided to verify the effectiveness of the proposed PWM methods.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1889-1900
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• 2018

Harmonic current mitigation is vital in power distribution networks owing to the inflow of nonlinear loads, distributed generation, and renewable energy sources. The active power filter (APF) is the current electrical equipment that can dynamically compensate for harmonic distortion and eliminate asymmetrical loads. The compensation performance of an APF largely depends on the control strategy applied to the voltage source inverter (VSI). Model predictive control (MPC) has been demonstrated to be one of the effective control approaches to providing fast dynamic responses. This approach covers different types of power converters due to its several advantages, such as flexible control scheme and simple inclusion of nonlinearities and constraints within the controller design. In this study, a finite control set-MPC technique is proposed for the control of VSIs. Unlike conventional control methods, the proposed technique uses a discrete time model of the shunt APF to predict the future behavior of harmonic currents and determine the cost function so as to optimize current errors through the selection of appropriate switching states. The viability of this strategy in terms of harmonic mitigation is verified in MATLAB/Simulink. Experimental results show that MPC performs well in terms of reduced total harmonic distortion and is effective in APFs.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.145-148
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• 2015

In this letter, we present a new linearization method for a voltage controlled oscillator (VCO)-based quantizer in an analog-to-digital converter (ADC). The nonlinearity of the VCO generates unwanted harmonic spurs and reduces the signal-to-noise and distortion ratio (SNDR) of the VCO-based quantizer. This letter suggests a frequency-to-current feedback method to effectively suppress harmonic distortion. The proposed method decreases the harmonic spurs by more than 53 dB. And a VCO-based quantizer employing the proposed linearization method achieves a high SNDR of 74.1 dB.

• Proceedings of the KIEE Conference
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• 2000.07e
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• pp.74-78
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• 2000

In this paper a switching control circuit for shaping the line current and reducing the total harmonics distortion in the boost converter is presented. To solve the problems of performance degradation due to pulse waveform in the input current, the boost converter in which the harmonic distortion in the input current is reduced using a 3th harmonic-injected PWM is proposed. Finally, Simulation and experimental results of boost converter with 5[kHz] switching frequency are presented and correction of power factor and reduction of total harmonic distortion was established.