• KSII Transactions on Internet and Information Systems (TIIS)
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• 제17권6호
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• pp.1600-1619
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• 2023

Organizations and other institutions have recently started using cloud service providers to store and share information in light of the Internet of Things (IoT). The major issues with this storage are preventing unauthorized access and data theft from outside parties. The Block chain based Security Sharing scheme with Data Access Control (BSSDAC) was implemented to improve access control and secure data transaction operations. The goal of this research is to strengthen Data Access Control (DAC) and security in IoT applications. To improve the security of personal data, cypher text-Policy Attribute-Based Encryption (CP-ABE) can be developed. The Aquila Optimization Algorithm (AOA) generates keys in the CP-ABE. DAC based on a block chain can be created to maintain the owner's security. The block chain based CP-ABE was developed to maintain secures data storage to sharing. With block chain technology, the data owner is enhancing data security and access management. Finally, a block chain-based solution can be used to secure data and restrict who has access to it. Performance of the suggested method is evaluated after it has been implemented in MATLAB. To compare the proposed method with current practices, Rivest-Shamir-Adleman (RSA) and Elliptic Curve Cryptography (ECC) are both used.

• 신재생에너지
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• 제3권4호
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• pp.69-76
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• 2007

In this paper, a PV multi-string PCS with a grid-connection is proposed. An improved MPPT algorithm for the PV multi-string PCS is suggested. Each PV string has its own MPP tracker and the proposed MPPT algorithm prevents LMPP tracking due to power ripple. In the PV PCS with single-phase inverter has a large current ripple at twice the grid frequency. The current ripple reduction algorithm without external component is suggested. Also, this paper proposes a simple control method to achieve sharing of the PV string voltage and current among the interleaved parallel boost converters. All algorithms and controllers are implemented on a single-chip microcontroller. Experimental results obtained on a 3kW prototype show high performance of the proposed PV multi-string PCS.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 하계학술대회 논문집
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• pp.451-455
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• 1991

The PWM control technique is proposed which can eliminate the harmonic components of the nonsinusoidal ac line current such as the current of 6-phase rectifier by injecting PWM current. TSC(Time-Sharing Control) is adopted to avoid the unbalance between three PWM injection currents at the three-phase system. Also a new power circuit for three-phase filter is suggested for realizing the proposed PWM control technique. The operation characteristics are investigated theoretically and experimentally to show the feasibility of the optimized injection method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 A
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• pp.556-558
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• 1994

This paper proposes a new converter that can reduce the harmonics like conventional 12-pulse dual thyrister converters with the input transformers. Both the bridges are controlled with the shifted firing angle and connected through current sharing reactors. Using the center tapped reactor, the DC link current is controlled with the different two values in order to make the input current waveform 12 pulses.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 추계학술대회 논문집
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• pp.255-258
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• 2007

In this paper, a PV multi-string PCS with a grid-connection is proposed. An improved MPPT algorithm for the PV multi-string PCS is suggested. Each PV string has its own MPP tracker and the proposed MPPT algorithm prevents LMPP tracking due to power ripple. In the PV PCS with single-phase inverter has a large current ripple at twice the grid frequency. The current ripple reduction algorithm without external component is suggested. Also, this paper proposes a simple control method to achieve sharing of the PV string voltage and current among the interleaved parallel boost converters. All algorithms and controllers are implemented on a single-chip microcontroller. Experimental results obtained on a 3kW prototype show high performance of the proposed PV multi-string PCS.

• Journal of Power Electronics
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• 제12권2호
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• pp.258-267
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• 2012

An interleaved single-stage AC/DC converter with a boost converter and an asymmetrical half-bridge topology is presented to achieve power factor correction, zero voltage switching (ZVS) and load voltage regulation. Asymmetric pulse-width modulation (PWM) is adopted to achieve ZVS turn-on for all of the switches and to increase circuit efficiency. Two ZVS half-bridge converters with interleaved PWM are connected in parallel to reduce the ripple current at input and output sides, to control the output voltage at a desired value and to achieve load current sharing. A center-tapped rectifier is adopted at the secondary side of the transformers to achieve full-wave rectification. The boost converter is operated in discontinuous conduction mode (DCM) to automatically draw a sinusoidal line current from an AC source with a high power factor and a low current distortion. Finally, a 240W converter with the proposed topology has been implemented to verify the performance and feasibility of the proposed converter.

• E2M - 전기 전자와 첨단 소재
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• 제10권4호
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• pp.320-326
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• 1997

The stability of Bi-based superconducting wires cooled by a cryocooler was studied by considering the temperature dependency of critical current and electrical resistivity. The critical current measured in 23 K was about 7 times higher than that measured in liquid nitrogen of 77 K. The stability behavior of Bi based multifilament wires subjected to a thermal disturbance, which was simulated with a electric heater, was investigated by measuring the variation of voltage drop with time. Current sharing was occurred, and recovery to superconductivity was measured in the wire after removing heater power.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제53권6호
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• pp.359-367
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• 2004

The switched reluctance motor(SRM) has considerable potential for industrial applications because of its high result lily as a result of the absence of rotor windings. In some applications with SRM, paralleling strategy is often used for cost saving, increasing of current capacity and system reliability. A SRM inverter has very low ,switching frequency. This results in reducing the burden for a high-speed of the gate-amp interface circuit. and the linearity of optocoupler is used to protect the instantaneous peak current for the stable operation. In this paper, series resistor is used to equal the current sharing of each switching device and a linear gate-amp is proposed to protect the instantaneous peak current which occurs in transient state. The proposed paralleling strategy is verified by experimental results.

• 조명전기설비학회논문지
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• 제22권12호
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• pp.157-163
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• 2008

다상 교호 컨버터에서 인덕턴스가 불일치 할 때 첨두전류 제어기를 사용하는 경우에 각 상의 평균 전류는 동일하지 않다. 본 논문에서는 각 상의 인덕턴스가 불일치한 경우에 첨두전류 모드에서 평균전류가 동일해지는 전류분배 제어기를 제안한다 제어기는 과도상태에서도 전류의 평형이 잘 이루어질 수 있도록 설계한다. 제안된 방법을 2상과 4상 교호 승압컨버터에 적용시켰으며, 실험 결과를 통해 인덕턴스가 불일치한 경우에도 첨두전류 모드에서 전류평형이 잘 이루어짐을 보인다.