• 한국멀티미디어학회논문지
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• 제21권9호
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• pp.1068-1075
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• 2018

We propose a method for driving loudspeakers from class D audio power amplifiers in current mode, instead of in conventional voltage mode, which was impossible with the feedback circuitry. Unlike analog audio amplifiers, Class D audio power amplifiers have signal delay between the input and output signals, which makes it difficult to apply the feedback circuitry for current-mode driving. The idea of the pre-distortion scheme used for the compensation of the non-linearity of RF power amplifiers is adapted to remedy the impedance variation effect of the loudspeakers for current driving. The method uses the speaker model for the pre-distorter to compensate for the speaker impedance variation with frequency. The simulation and test results confirms the validity of the proposed method.

• 한국전자파학회논문지
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• 제22권12호
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• pp.1060-1068
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• 2011

본 논문에서는 900 MHz 대역에서 동작하는 전류 모드 Class-D(Current-Mode Class-D: CMCD) 전력 증폭기를 설계 및 제작하고 특성을 분석하였다. 차동 구조에 의해 짝수차 고조파 성분이 제거된다는 점에 착안하여 출력단의 일반적인 CMCD 회로의 병렬 공진기를 제거하고 inverse class-F 전력 증폭기를 push-pull 구조로 연결하여 CMCD 전력 증폭기를 설계하였다. 로드-풀 기법을 이용하여 GaN 소자 기반의 inverse class-F 및 이를 적용한 CMCD 전력 증폭기를 설계 및 제작하였다. 제작한 CMCD는 34.2 dBm의 출력과 64.5 %의 드레인 효율을 가지며, 이는 출력측에 공진기 구조를 가지는 일반적인 CMCD 전력 증폭기의 드레인 효율과 비교했을 때 13.6 %의 효율 향상을 가진다.

• Journal of Power Electronics
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• 제14권4호
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• pp.641-648
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• 2014

This paper presents the design considerations and analysis for an interleaved boundary conduction mode power factor correction buck converter. A thorough analysis of the harmonic content of the AC line current is presented to examine the allowable voltage gain (K value) for meeting the EN61000-3-2, Class D standard while maximizing efficiency. The results of the harmonic analysis are used to derive the required value of K and therefore the output voltage necessary to meet the class D requirements for a given AC line voltage. The discussed design consideration and harmonic current analysis are verified on a 300W universal line experimental prototype converter with an 80V output. The measured efficiencies remain above 96% down to 20% of the full load. The input current harmonics also meet the IEC61000-3-2 (class D) standard.

• 한국전자파학회논문지
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• 제23권5호
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• pp.624-631
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• 2012

본 논문은 Guanella의 1:1 transmission-line transformer와 harmonic filtering 방식을 이용한 13.56 MHz 고효율 전류 모드 D급(CMCD) 전력증폭기를 제안한다. 출력 정합 네트워크에 기존의 D급 전력증폭기의 부하 네트워크를 변형하여 harmonic filtering 방식을 포함시킴으로써 낮은 2차와 3차 고조파 특성을 얻었다. 제작된 CMCD 전력증폭기는 13.56 MHz의 CW 입력 신호를 사용하여 측정하였을 때, 13.4 dB의 전력 이득을 가지며, 44.4 dBm의 출력에서 84.6 %의 높은 PAE 특성을 나타내었다. 같은 출력에서 2차 3차 고조파는 각각 -50.3 dBc와 -46.4 dBc를 나타냈다.

• 한국전자파학회논문지
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• 제15권6호
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• pp.540-547
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• 2004

본 논문에서는 900 MHz대역에서 70 % 이상의 고효율을 갖는 전류 모드 D급 전력증폭기를 설계, 제작하였다. 푸시-풀 B급 전력증폭기의 구조를 기초로 하여 병렬 고조파 컨트롤 회로를 적용하여, 기존 D급 전력증폭기의 큰 손실 요인이었던 소자 내 커패시턴스의 충, 방전에 의한 전력 손실을 최소화하였다. 측정결과, 900 MHz 대역, 출력전력 3.2 W에서 73 % 전력 부가 효율, 그리고 출력전력 5 W에서 72 % 전력 부가 효율을 각각 얻었으며 DC 전력에 따라 출력의 크기가 선형적으로 변화하는 D급 전력증폭기의 특성을 확인하였다.

• 한국항행학회논문지
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• 제23권2호
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• pp.166-171
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• 2019

본 논문은 6.78 MHz무선전력전송 송신기의 전송 효율을 높이고 송수신 코일 간격 변화에도 안정적 특성을 확보하기 위해 전류 모드 클래스 D 전력증폭기를 설계한다. 선형증폭기의 이론적인 효율을 제한하는 트랜지스터의 기생 커패시터 성분에 의한 손실을 적게 만들어 전력증폭기의 효율을 향상시킨다. 회로 설계 시뮬레이터를 이용하여 고효율 증폭기를 설계하고 부하 임피던스 변화에 따른 전력 출력, 효율 특성을 시뮬레이션하여 검증하였다. 시뮬레이션에서 DC 바이어스 30 V일 때 42.1 dBm의 출력과 95%의 효율을 갖도록 설계하였다. 전력증폭기를 제작하여 42.1 dBm (16 W)의 출력에서 91%의 효율을 보였다. 드론 무선전력전송에 적용될 송수신 코일을 제작하였으며, 송수신 코일 간격에 따른 부하변화에 따라 전력부가효율이 최대 88% 이고 출력전력 $42.1dBm{\pm}1.7dB$의 특성을 나타내었다.

• ETRI Journal
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• 제34권6호
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• pp.885-891
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• 2012

This paper proposes a high-efficiency power amplifier (PA) with uneven bias. The proposed amplifier consists of a driver amplifier, power stages of the main amplifier with class AB bias, and an auxiliary amplifier with class C bias. Unlike other CMOS PAs, the amplifier adopts a current-mode transformer-based combiner to reduce the output stage loss and size. As a result, the amplifier can improve the efficiency and reduce the quiescent current. The fully integrated CMOS PA is implemented using the commercial Taiwan Semiconductor Manufacturing Company 0.18-${\mu}m$ RF-CMOS process with a supply voltage of 3.3 V. The measured gain, $P_{1dB}$, and efficiency at $P_{1dB}$ are 29 dB, 28.1 dBm, and 37.9%, respectively. When the PA is tested with 54 Mbps of an 802.11g WLAN orthogonal frequency division multiplexing signal, a 25-dB error vector magnitude compliant output power of 22 dBm and a 21.5% efficiency can be obtained.

• Journal of electromagnetic engineering and science
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• 제14권3호
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• pp.284-292
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• 2014

This paper presents a characteristic evaluation of commercial gallium nitride (GaN) transistors having two different gate-lengths of $0.4-{\mu}m$ and $0.25-{\mu}m$ in the design of a class-S power amplifier (PA). Class-S PA is operated by a random pulse-width input signal from band-pass delta-sigma modulation and has to deal with harmonics that consider quantization noise. Although a transistor having a short gate-length has an advantage of efficient operation at higher frequency for harmonics of the pulse signal, several problems can arise, such as the cost and export license of a $0.25-{\mu}m$ transistor. The possibility of using a $0.4-{\mu}m$ transistor on a class-S PA at 955 MHz is evaluated by comparing the frequency characteristics of GaN transistors having two different gate-lengths and extracting the intrinsic parameters as a shape of the simplified switch-based model. In addition, the effectiveness of the switch model is evaluated by currentmode class-D (CMCD) simulation. Finally, device characteristics are compared in terms of current-mode class-S PA. The analyses of the CMCD PA reveal that although the efficiency of $0.4-{\mu}m$ transistor decreases more as the operating frequency increases from 955 MHz to 3,500 MHz due to the efficiency limitation at the higher frequency region, it shows similar power and efficiency of 41.6 dBm and 49%, respectively, at 955 MHz when compared to the $0.25-{\mu}m$ transistor.

• Journal of Electrical Engineering and Technology
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• 제13권3호
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• pp.1251-1264
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• 2018

The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for $220-V_{rms}/50-Hz$ utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load.

• 전자공학회논문지C
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• 제34C권9호
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• pp.1-9
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• 1997

Novel class A CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well standard CMOS process for high-frequency current-mode signal processing were developed. The CCII consists of a regulated current-cell for the voltage input and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated cCII show that the current input impedance is 308 .ohm. and the 3-dB cutoff frequency when used as a voltage amplifier extends beyond 10MHz. The linear dynamic ranges of voltage and current are from -0.5V to 1.5V and from -100.mu.A to +120.mu.A for supply voltage V$\_$DD/ = -V$\_$SS/=2.5V, respectively. The power dissipation is 2 mW and the active chip area is 0.2 * 0.2 [mm$\^$2/].