• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.29.1-29.1
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• 2009

반도체 공정에서의 금속 배선 공정은 매우 중요한 공정 중 하나이다. 기존에 사용되던 알루미늄이 한계에 다다르면서, 대체 재료로 사용되고있는 구리는 낮은 비저항, 높은 열전도도, 우수한 electromigration(EM)저항특성 등을 바탕으로 차세대 nano-scale집적회로의 interconnect application에 적합한 금속재료로서 각광받고 있다. Electroplating을 위한 구리 seed layer CVD 공정은 타 공정에 비해 step coverage가 우수한 막을 증착할 수 있어 고집적 소자의 구현이 가능하다. 본 연구에 이용된 2가 전구체 Cu(dmamb)2는 높은 증기압과 높은 활성화 에너지를 가짐으로서 열적안정성 및 보관안정성이 우수하며, 플루오르를 함유하지 않아 친환경적이다. 구리 증착 전 기판에 plasma 처리를 하면 표면 morphology가 변함에 따라 표면 에너지가 변화하고, 이는 구리의 2차원 성장에 유리하게 작용할 것으로 여겨진다. Plasma의 조건변화에 따른 기판의 morphology 변화 및 성막된 구리의 특성 변화를 분석하였다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.261-278
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• 2003

Concepts.Wafer-Level Chip-Scale Concept with Handling Substrate.Low Accuracy Placement Layout with Isolation Trench.Possible Pitch of Interconnections down to $10{\mu}{\textrm}{m}$ (Sn-Grains).Wafer-to-Wafer Equipment Adjustment Accuracy meets this Request of Alignment Accuracy (+/-1.5 ${\mu}{\textrm}{m}$).Adjustment Accuracy of High-Speed Chip-to-Wafer Placement Equipment starts to meet this request.Face-to-Face Modular / SLID with Flipped Device Orientation.interchip Via / SLID with Non-Flipped Orientation SLID Technology Features.Demonstration with Copper / Tin-Alloy (SLID) and W-InterChip Vias (ICV).Combination of reliable processes for advanced concept - Filling of vias with W as standard wafer process sequence.No plug filling on stack level necessary.Simultanious formation of electrical and mechanical connection.No need for underfiller: large area contacts replace underfiller.Cu / Sn SLID layers $\leq$ $10{\mu}{\textrm}{m}$ in total are possible Electrical Results.Measurements of Three Layer Stacks on Daisy Chains with 240 Elements.2.5 Ohms per Chain Element.Contribution of Soldering Metal only in the Range of Milliohms.Soldering Contact Resistance ($0.43\Omega$) dominated by Contact Resistance of Barrier and Seed Layer.Tungsten Pin Contribution in the Range of 1 Ohm

• Journal of Electrochemical Science and Technology
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• v.7 no.2
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• pp.132-138
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• 2016

In this study, we report the fabrication of functional complex fibers, which have been studied widely globally for numerous applications. Here, we fabricated conductive complex fibers with antibacterial properties by coating metal ions on the surface of plastic (polypropylene) fibers using the electroless and electrochemical deposition. First, we polished the polypropylene melt-blown fiber surface and obtained an absorbing Pd seed layer on its surface. Subsequently, we substituted the Pd with Cu. Bis-3-sulfopropyl-disulfide disodium salt (SPS), polyethylene glycol (PEG), and ethylene thiourea (ETU) were used as the brightener, carrier, and leveler, respectively for the electroplating. We focused on most achieving the stable plating condition to remove dendrites, which are normally during electroplating metals so that smooth layer is formed on the fiber surface. The higher the amount of SPS, the higher was the extent of irregular plate-like growth. Many irregularities in the form of round spheres were observed with increase in the amount of PEG and ETU. Hence, when the additives were used separately, a uniform coating could not be obtained. A stable coating was obtained when the three additives were combined and a uniform 5-9 μm thick copper layer with a stable morphology could be obtained around the fiber. We believe that our results can be applied widely to obtain conductive fibers with antibacterial properties and are useful in aiding research on conductive lightweight composite fibers for application in information technology and robotics.

• Korean Journal of Materials Research
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• v.30 no.4
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• pp.160-168
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• 2020

The current density in copper electroplating is directly related with the productivity; then, to increase the productivity, an increase in current density is required. This study is based on an analysis of changes in surface characteristics and mechanical properties by applying the addition of Alcian Blue (AB, C₅₆H₆₈Cl₄CuN₁₆S₄). The amount of Alcian Blue in the electrolytes is changed from 0 to 100 ppm. When Alcian Blue is added at 20 ppm, a seed layer is formed homogeneously on the surface at the initial stage of nucleation. However, crystals electroplated in electrolytes with more than 40 ppm of Alcian Blue are observed to have growth in the vertical direction on the surface and the shapes are like pyramids. This tendency of initial nucleation formation causes protrusions when the thickness of copper foil is 12 ㎛. Thereafter, a lot of extrusions are observed on the group of 100 ppm Alcian Blue. Tensile strength of groups with added Alcian Blue increased by more than 140% compare to no-addition group, but elongation is reduced. These results are due to the decrease of crystal size and changes of prior crystal growth plane from (111) and (200) to (220) due to Alcian Blue.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.23.2-23.2
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• 2009

기존에 사용되었던 알루미늄 배선 공정은 공정의 배선 크기가 줄어들면서 한계에 다다르고 있다. 따라서 이를 대체하기 위해 여러 가지 새로운 방법들이 고안되고 있으며, 그중 알루미늄을 비저항이 낮고 EM(electro-migration) 저항성이 뛰어난 구리로 대체하려는 연구가 진행되고 있다. 구리 배선은 이미 electroplating 공정을 이용해 산업에 적용되고 있으며, seed layer로는 sputtering 법을 이용하고 있다. 하지만 sputtering 을 포함한 PVD 법은 대부분 종횡비나 단차 피복도가 좋지 않기 때문에 이를 CVD로 교체한다면 많은 장점을 가질 수 있다. 하지만 CVD 공정을 진행하기 위해서는 많은 문제점들이 있는데, 이중 전구체에 대한 문제도 빼놓을 수 없는 이슈이다. Cu(dmamb)2 는 기존에 사용하던 $\beta$-diketonate 계열의 전구체보다 화학적으로 많은 장점을 가지고 있어, CVD 공정에 적합하다. 이에 따라 구리 박막 증착의 공정 조건을 설계하고, 고품질의 박막을 증착하기 위한 다양한 처리법을 고안하여 증착 실험을 진행하였다. 기본적으로 구리는 확산력이 좋아 실리콘계열의 기판에서 확산력이 매우 좋아 기판 내로 확산되기 때문에 이를 방지하기 위하여 Ta, Ti 계열의 박막을 사용하여 확산을 방지하고 있다. 따라서 전이 금속 박막의 표면과 증착 분위기 등을 고려하여 구리를 증착하였으며, 표면의 미세구조 및 성분을 FESEM 등을 통해 분석하였다.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.45-50
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• 2006

Copper via filling is the important factor in 3-D stacking interconnection of SiP (system in package). As the packaging density is getting higher, the size of via is getting smaller. When DC electroplating is applied, a defect-free hole cannot be obtained in a small size via hole. To prevent the defects in holes, pulse and pulse reverse current was applied in copper via filling. The holes, $20\and\;50{\mu}m$ in diameter and $100{\sim}190\;{\mu}m$ in height. The holes were prepared by DRIE method. Ta was sputtered for copper diffusion barrier followed by copper seed layer IMP sputtering. Via specimen were filled by DC, pulse and pulse-reverse current electroplating methods. The effects of additives and current types on copper deposits were investigated. Vertical and horizontal cross section of via were observed by SEM to find the defects in via. When pulse-reverse electroplating method was used, defect free via were successfully obtained.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.129-134
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• 2005

Electroplating copper is the important role in formation of 3D stacking interconnection in SiP (System in Package). The I-V characteristics curves are investigated at different electrolyte conditions. Inhibitor and accelerator are used simultaneously to investigate the effects of additives. Three different sizes of via are tested. All via were prepared with RIE (reactive ion etching) method. Via's diameter are 50, 75, $100{\mu}m$ and the height is $100{\mu}m$. Inside via, Ta was deposited for diffusion barrier and Cu was deposited fer seed layer using magnetron sputtering method. DC, pulse and pulse revere current are used in this study. With DC, via cannot be filled without defects. Pulse plating can improve the filling patterns however it cannot completely filled copper without defects. Via was filled completely without defects using pulse-reverse electroplating method.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.339-339
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• 2002

In the RABiTS approach to coated conductor development, successful (both economic and technological) depends on the refinement and optimization of each of three important components: the metal tape substrate, the buffer layer(s), and the HTS layer. Here we will report on the ORNL approach and progress in each of these areas. - Most applications will require metal tapes with low magnetic hysteresis, mechanical strength, and excellent crystalline texture. Some of these requirements are competing. We report on progress in obtaining a good combination of these characteristics on metal alloys of Ni-Cr and Ni-W. - The deposition of appropriate buffer layers is a crucial step. Recently, base research has shown that the presence of a stable sulfur superstructure present on the metal surface is needed for the nucleation and epitaxial growth of vapor-deposited seed buffer layers such as YSZ, CeO$_2$ and SrTiO$_3$. We report on the details and control of this superstructure for nickel tapes, as well as recent results for Cu and Ni-13%Cr. - Processes for deposition of the HTS coating must economically provide large values of the figure-of-merit for conductors, current x length. At ORNL, we have devoted efforts to a precursor/post-annealing approach to YBCO coatings, for which the deposition and reaction steps are separate. We describe motivation for and progress toward developing this approach. - Finally, we address some issues for the implementation of coated conductors in real applications, including the need for texture control and electrical stabilization of the HTS coating.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.13-16
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• 2013

A lot of various researches have been going on to use heat spreader for LED module. Nano porous aluminum anodic oxide (AAO) applied LED, which is produced from anodization, is easy and economically advantageous. Convensional LED module is consist of aluminum/adhesive/copper circuit. The polymer adhesive in this module is used as heat spreader. However the thermal emission of LED component is degraded because of low heat conductivity of polymer and also reliability of LED component is reduced. Therefore, AAO in this work was applied to heat spreader of LED module which has higher heat conductivity compare to polymer. Bonding strength between AAO and copper circuit was improved with Ti/Cu seed layer by copper sputtering process (DBC) before the bonding. And this copper circuit has been fabricated by electro plating method. Peel strength of AAO and copper circuit in this work showed range between 1.18~1.45 kgf/cm with anodizing process which is very suitable for high power LED application.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.33-38
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• 2001

We investigate the via-size dependance of as-electroplated- and reflow-bump shapes for realizing both high-density and high-aspect ratio of solder bump. The solder bump is fabricated by subsequent processes as follows. After sputtering a TiW/Al electrode on a 5-inch Si-wafer, a thick photoresist for via formation it obtained by multiple-codling method and then vias with various diameters are defined by a conventional photolithography technique using a contact alinger with an I-line source. After via formation the under ball metallurgy (UBM) structure with Ti-adhesion and Cu-seed layers is sputtered on a sample. Cu-layer and Sn/pb-layer with a competition ratio of 6 to 4 are electroplated by a selective electroplating method. The reflow-bump diameters at bottom are unchanged, compared with as-electroplated diameters. As-electroplated- and reflow-bump shapes, however, depend significantly on the via size. The heights of as-electroplated and reflow bumps increase with the larger cia, while the aspect ratio of bump decreases. The nearest bumps may be touched by decreasing the bump pitch in order to obtain high-density bump. The touching between the nearest bumps occurs during the overplating procedure rather than the reflowing procedure because the mushroom diameter formed by overplating is larger than the reflow-bump diameter. The arrangement as zig-zag rows can be effective for realizing the flip-chip-interconnect bump with both high-density and high-aspect ratio.