• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.114-121
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• 2003

Through comparing stress state of TEOS and SiLK-embedded structures, the effect of low-k materials on stress and stress distribution in via-line structures were investigated using three-dimensional finite element analyses. In the case of TEOS-embedded via-line structures, hydrostatic stress was concentrated at the via and the top of the lines, where the void was suspected to nucleate. On the other hand, in the via-line structures integrated with SiLK, large von-Mises stress is maintained at the via, thus deformation of via is expected as the main failure mode. A good correlation between the calculated results and experimentally observed failure modes according to dielectric materials was obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.528-528
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• 2007

Cu CMP widely has been using for the formation of multilevel metal interconnects by the Cu damascene process. And lower dielectric constant materials are required for the below 45nm technology node. As the dielectric constant of dielectric materials are smaller, the strength of dielectric materials become weaker. Therefore these materials are easily damaged by high down pressure during conventional CMP. Also, technical problems such as surface scratches, delamination, dishing and erosion are also occurred. In order to overcome these problems in CMP, the ECMP (electro-chemical mechanical planarization) has been introduced. In this process, abrasive free electrolyte, soft pad and low down force were used. The electrolyte is one of important factor to solve these problems. Also, additives are required to improve the removal rate, uniformity, surface roughness, defects, and so on. In this study, KOH and $NaNO_3$ based electrolytes were used for Cu ECMP and the electrochemical behavior was evaluated by the potentiostat. Also, the Cu surface was observed by SEM as a function of applied voltage and chemical concentration.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.81-81
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• 2007

Chemical mechanical polishing (CMP) 공정은 deep 서브마이크론 집적회로의 다층배선구조률 실현하기 위해 inter-metal dielectric (IMD), inter-layer dielectric layers (ILD), pre-metal dielectric (PMD) 층과 같은 절연막 외에도 W, Al, Cu와 같은 금속층을 평탄화 하는데 효과적으로 사용되고 있으며, 다양한 소자 제작 및 새로운 물질 등에도 광범위하게 응용되고 있다. 하지만 Cu damascene 구조 제작으로 인한 CMP 응용 과정에서, 기계적으로 깨지기 쉬운 65 nm의 소자 이하의 구조에서 새로운 저유전상수인 low-k 물질의 도입으로 인해 낮은 하력의 기계적 연마가 필요하게 되었다. 본 논문에서는 전기화학적 기계적 연마 적용을 위해, I-V 특성 곡선을 이용하여 active, passive, transient, trans-passive 영역의 전기화학적 특성을 알아보았으며, Cu 막의 표면 형상을 알아보기 위해 scanning electron microscopy (SEM) 측정과 energy dispersive spectroscopy (EDS) 분석을 통해 금속 화학적 조성을 조사하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.78-78
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• 2007

In semiconductor devices, Cu has been used for the formation of multilevel metal interconnects by the damascene technique. Also lower dielectric constant materials is needed for the below 65 nm technology node. However, the low-k materials has porous structure and they can be easily damaged by high down pressure during conventional CMP. Also, Cu surface are vulnerable to have surface scratches by abrasive particles in CMP slurry. In order to overcome these technical difficulties in CMP, electro-chemical mechanical planarization (ECMP) has been introduced. ECMP uses abrasive free electrolyte, soft pad and low down-force. Especially, electrolyte is an important process factor in ECMP. The purpose of this study was to characterize KOH and $KNO_3$ based electrolytes on electro-chemical mechanical. planarization. Also, the effect of additives such as an organic acid and oxidizer on ECMP behavior was investigated. The removal rate and static etch rate were measured to evaluate the effect of electro chemical reaction.