• Title/Summary/Keyword: Cu contact

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Electrical Properties of CuPc Field-effect Transistor with Different Metal Electrodes (금속 전극 변화에 따른 CuPc Field-effect Transistor의 전기적 특성)

  • Lee, Ho-Shik;Park, Yong-Pil
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.11a
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    • pp.494-495
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    • 2007
  • Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different metal electrode. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature. The source and drain electrodes were used an Au and Al materials. The CuPc thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET with different electrode materials.

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Fabrication and Electrical Properties of CuPc FET with Different Substrate Temperature (CuPc FET의 기판온도에 따른 제작 및 전기적 특성 연구)

  • Lee, Ho-Shik;Park, Yong-Pil;Lim, Eun-Ju;Iwamot, Mistumasa
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.06a
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    • pp.488-489
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    • 2007
  • Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different substrate temperature. The CuPc FET device was made a top-contact type and the substrate temperature was room temperature and $150^{\circ}C$. The CuPc thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed a typical current-voltage (I-V) characteristics in CuPc FET.

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Analysis of Lattice constants change for study of W-C-N Diffusion (W-C-N 확산방지막의 격자상수 변화 분석을 통한 특성 연구)

  • Kim, Soo-In;Lee, Chang-Woo
    • Journal of the Korean Vacuum Society
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    • v.17 no.2
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    • pp.109-112
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    • 2008
  • The miniaturization of device size and submicron process causes serious problems in conventional metallization due to the solubility of silicon and metal at the interface, such as an increasing contact resistance in the contact hole and interdiffusion between metal and silicon. Moreover, the interaction between Cu and Si is so strong and detrimental to the electrical performance of Si even at temperatures below $200^{\circ}C$. Therefore it is necessary to implement a barrier layer between Cu and Si. So we study W-C-N diffusion barrier for prevent Cu diffusion as a function of $N_2$ gas flow and thermal stability. Especially, we also study the W-C-N diffusion barrier for analyzing the change of lattice constants.

Interdiffusion in Cu/Capping Layer/NiSi Contacts (Cu/Capping Layer/NiSi 접촉의 상호확산)

  • You, Jung-Joo;Bae, Kyoo-Sik
    • Korean Journal of Materials Research
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    • v.17 no.9
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    • pp.463-468
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    • 2007
  • The interdiffusion characteristics of Cu-plug/Capping Layer/NiSi contacts were investigated. Capping layers were deposited on Ni/Si to form thermally-stable NiSi and then were utilized as diffusion barriers between Cu/NiSi contacts. Four different capping layers such as Ti, Ta, TiN, and TaN with varying thickness from 20 to 100 nm were employed. When Cu/NiSi contacts without barrier layers were furnace-annealed at $400^{\circ}C$ for 40 min., Cu diffused to the NiSi layer and formed $Cu_3Si$, and thus the NiSi layer was dissociated. But for Cu/Capping Layers/NiSi, the Cu diffusion was completely suppressed for all cases. But Ni was found to diffuse into the Cu layer to form the Cu-Ni(30at.%) solid solution, regardless of material and thickness of capping layers. The source of Ni was attributed to the unreacted Ni after the silicidation heat-treatment, and the excess Ni generated by the transformation of $Ni_2Si$ to NiSi during long furnace-annealing.

Local Current Distribution in a Ferromagnetic Tunnel Junction Fabricated Using Microwave Excited Plasma Method (마이크로파 여기 프라즈마법으로 제조한 강자성 터널링 접합의 국소전도특성)

  • Yoon, Tae-Sick;Kim, Cheol-Gi;Kim, Chong-Oh;Masakiyo Tsunoda;Migaku Takahashi;Ying Li
    • Journal of the Korean Magnetics Society
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    • v.13 no.2
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    • pp.47-52
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    • 2003
  • Ferromagnetic tunnel junctions were fabricated by dc magnetron sputtering and plasma oxidation process. The local transport properties of the ferromagnetic tunnel junctions were studied using contact-mode Atomic Force Microscopy (AFM) and the local current-voltage analysis. Tunnel junctions with the structure of sub./Ta/Cu/Ta/NiFe/Cu/Mn$\_$75/Ir$\_$25//Co$\_$70/Fe$\_$30//Al-oxide were prepared on thermally oxidized Si wafers. Al-oxide layers were formed with microwave excited plasma using radial line slot antenna (RLSA) for 5 and 7 sec. Kr gas was used as the inert gas mixed with $O_2$ gas for the plasma oxidization. No correlation between topography and current image was observed while they were measured simultaneously. The local current distribution was well identified with the distribution of local barrier height. Assuming the gaussian distribution of the local barrier height, the ferromagnetic tunnel junction with longer oxidation time was well fitted with the experimental results. As contrast, in the case of the shorter time oxidation junction, the current mainly flow through the low barrier height area for its insufficient oxygen. Such leakage current might result in the decrease of tunnel magnetoresistance (TMR) ratio.

Stress Analysis and Lead Pin Shape Design in PGA (Pin Grid Array) Package (PGA (Pin Grid Array) 패키지의 응력해석 및 Lead Pin 형상설계)

  • Cho, Seung-Hyun;Choi, Jin-Won
    • Journal of the Microelectronics and Packaging Society
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    • v.18 no.2
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    • pp.29-33
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    • 2011
  • Research about the geometry design of lead pin was carried based on the normal or shear stress of the interface between a lead pin and a PCB in terms of delamination failure. The taguchi method with four design factors of three levels and FEA(Finite element Analysis) are carried under $20^{\circ}$ bending and 50 ${\mu}m$ tension of lead pin. The contact width, d2, between head round and copper pad in PCB is the highest affection factor among design factors by analysis of contribution analysis. Equivalent von Mises stress of 18.7% reduction design is obtained by the parameter design of the taguchi method. Maximum normal stress occurred at contact position between solder outer surface and a Cu pad in PCB. Also, maximum shear stress happened at contact position between solder outer surface and SR layer of PCB. From these calculated results, delamination of the PGA package may be occurred from outer interface of solder to inner interface of solder.

Effects of Surface Roughness on Contact Angle of Nanofluid Droplet (표면조도가 나노유체 액적의 접촉각에 미치는 영향)

  • Kim, Yeung Chan
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.37 no.6
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    • pp.559-566
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    • 2013
  • The effects of solid surface roughness on the contact angle of a nanofluid droplet were experimentally investigated. The experiments were conducted using the solid surface of a 10 mm cubic copper block and the nanofluid of water mixed with CuO nanoparticles. The experimental results showed that the contact angles of nanofluid droplets were lower than those of water droplets and that the contact angle of the nanofluid droplet increased with the solid surface roughness. Furthermore, it was found that the contact angles of water droplets on the solid surface quenched by both water and the nanofluid were lower than those of water droplets on the pure solid surface. However, significant differences were not observed between the contact angles on the solid surfaces quenched by water and the nanofluid.

Investigation of Effective Contact Resistance of ZTO-Based Thin Film Transistors

  • Gang, Yu-Jin;Han, Dong-Seok;Park, Jae-Hyeong;Mun, Dae-Yong;Sin, So-Ra;Park, Jong-Wan
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.543-543
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    • 2013
  • Thin-film transistors (TFTs) based on oxide semiconductors have been regarded as promising alternatives for conventional amorphous and polycrystalline silicon TFTs. Oxide TFTs have several advantages, such as low temperature processing, transparency and high field-effect mobility. Lots of oxide semiconductors for example ZnO, SnO2, In2O3, InZnO, ZnSnO, and InGaZnO etc. have been researched. Particularly, zinc-tin oxide (ZTO) is suitable for channel layer of oxide TFTs having a high mobility that Sn in ZTO can improve the carrier transport by overlapping orbital. However, some issues related to the ZTO TFT electrical performance still remain to be resolved, such as obtaining good electrical contact between source/drain (S/D) electrodes and active channel layer. In this study, the bottom-gate type ZTO TFTs with staggered structure were prepared. Thin films of ZTO (40 nm thick) were deposited by DC magnetron sputtering and performed at room temperature in an Ar atmosphere with an oxygen partial pressure of 10%. After annealing the thin films of ZTO at $400^{\circ}C$ or an hour, Cu, Mo, ITO and Ti electrodes were used for the S/D electrodes. Cu, Mo, ITO and Ti (200 nm thick) were also deposited by DC magnetron sputtering at room temperature. The channel layer and S/D electrodes were defined using a lift-off process which resulted in a fixed width W of 100 ${\mu}m$ and channel length L varied from 10 to 50 ${\mu}m$. The TFT source/drain series resistance, the intrinsic mobility (${\mu}i$), and intrinsic threshold voltage (Vi) were extracted by transmission line method (TLM) using a series of TFTs with different channel lengths. And the performances of ZTO TFTs were measured by using HP 4145B semiconductor analyzer. The results showed that the Cu S/D electrodes had a high intrinsic field effect mobility and a low effective contact resistance compared to other electrodes such as Mo, ITO and Ti.

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Formation of Ni-W-P/Cu Electrodes for Silicon Solar Cells by Electroless Deposition (무전해 도금을 이용한 Si 태양전지 Ni-W-P/Cu 전극 형성)

  • Kim, Eun Ju;Kim, Kwang-Ho;Lee, Duk Haeng;Jung, Woon Suk;Lim, Jae-Hong
    • Journal of the Korean institute of surface engineering
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    • v.49 no.1
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    • pp.54-61
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    • 2016
  • Screen printing of commercially available Ag paste is the most widely used method for the front side metallization of Si solar cells. However, the metallization using Ag paste is expensive and needs high temperature annealing for reliable contact. Among many metallization schemes, Ni/Cu/Sn plating is one of the most promising methods due to low contact resistance and mass production, resulting in high efficiency and low production cost. Ni layer serves as a barrier which would prevent copper atoms from diffusion into the silicon substrate. However, Ni based schemes by electroless deposition usually have low thermal stability, and require high annealing process due to phosphorus content in the Ni based films. These problems can be resolved by adding W element in Ni-based film. In this study, Ni-W-P alloys were formed by electroless plating and properties of it such as sheet resistance, resistivity, specific contact resistivity, crystallinity, and morphology were investigated before and after annealing process by means of transmission line method (TLM), 4-point probe, X-ray diffraction (XRD), and Scanning Electron Microscopy (SEM).