• Journal of Surface Science and Engineering
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• v.36 no.5
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• pp.386-392
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• 2003

The electroplating process for a solder bump which can be applied for a flip chip was studied. Si-wafer was used for an experimental substrate, and the substrate were coated with UBM (Under Bump Metallization) of Al(400 nm)/Cu(300 nm)Ni(400 nm)/Au(20 nm) subsequently. The compositions of the bump were Sn-Cu and eutectic Sn-Pb, and characteristics of two bumps were compared. Experimental results showed that the electroplated thickness of the solders were increased with time, and the increasing rates were TEX>$0.45 <\mu\textrm{m}$/min for the Sn-Cu and $ 0.35\mu\textrm{m}$/min for the Sn-Pb. In the case of Sn-Cu, electroplating rate increased from 0.25 to $2.7\mu\textrm{m}$/min with increasing current density from 1 to 8.5 $A/dm^2$. In the case of Sn-Pb the rate increased until the current density became $4 A/dm^2$, and after that current density the rate maintains constant value of $0.62\mu\textrm{m}$/min. The electro plated bumps were air reflowed to form spherical bumps, and their bonded shear strengths were evaluated. The shear strength reached at the reflow time of 10 sec, and the strength was of 113 gf for Sn-Cu and 120 gf for Sn-Pb.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.237-241
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• 2000

The effects of Si addition on the precipitation processes of in Al-Cu-Si alloy films were studied by the transmission electron microscopy. Deposition of an Al-1.5Cu-1.5Si (wt. %) film at $305^{\circ}C$ resulted in formation of fine, uniformly distributed spherical $\theta$-phase particles due to the precipitation of the $\theta$ and Si phase particles during deposition. For deposition at $435^{\circ}C$, fine $\theta$-phase particles precipitated during wafer cooldown, while coarse Si nodules formed at the sublayer interface during deposition. The film susceptibility to corrosion is discussed in relation to the film microstructure and deposition temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.537-537
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• 2008

Copper (Cu) has been widely used for interconnection structure in intergrated circuits because of its properties such as a low resistance and high resistance to electromigration compared with aluminuim. Damascene processing for the interconnection structure utilizes 2-steps chemical mechanical polishing(CMP). After polishing, the removal of abrasive particles on the surfaces becomes as important as the polishing process. In the paper, buffing process for the removal of colloidal silica from polished Cu wafer was proposed and demonstrated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.57-58
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• 2006

Chemical-mechanical planarization (CMP) of Cu has used currently in semiconductor process for multilevel metallization system. This process requires the application of a considerable down-pressure to the sample in the polishing, because porous low-k films used in the Cu-multilevel interconnects of 65nm technology node are often damaged by mechanical process. Also, it make possible to reduce scratches and contaminations of wafer. Electrochemical mechanical planarization (ECMP) is an emerging extension of CMP. In this study, the electrochemical mechanical polisher was manufactured. And the static and dynamic potentiodynamic curve of Cu were measured in KOH based electrolyte and then the suitable potential was found.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.865-871
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• 2014

Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.3
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• pp.59-65
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• 1999

In this paper, we had studied the possibility of application as Cu thin films from (hfac)Cu(VTMOS) which is very stable. Cu thin films had been studied as a function of deposition temperature. Substrates used in the experiment were PVD TiN on Si wafer. Deposition conditions were as follow : deposition temperature $50^{\circ}C$. Cu thin films were analyzed by AES, four point probe, XRD and SEM. All of deposited films were very pure and some favoring of <111> planes perpendicular to the substrate surface were observed. Cu thin films had two distinct growth rates at various deposition temperature. One is the surface reaction limited region below $200^{\circ}C$, and the other is the mass transport limited region above $200^{\circ}C$. The resistivity of deposited Cu thin films under the optimum deposition condition is $2.5mu\Omega.cm$ Thus, properties of deposited Cu thin films using (hfac)Cu(VTMOS) didn't show difference with Cu thin films from other precursors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.370-373
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical Planarization(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper depostion is a mature process from a historical point of view, but a very young process from a CMP persperspective. While copper electrodepostion has been used and stuidied for dacades, its application to Cu damascene wafer processing is only now ganing complete accptance in the semiconductor industry. The polishing mechanism of Cu CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper pasivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.4
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• pp.328-332
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• 2011

The formation of front metal contact silicon solar cells is required for low cost, low contact resistance to silicon surface. One of the front metal contacts is Ni/Cu plating that it is available to simply and inexpensive production to apply mass production. Ni is shown to be a suitable barrier to Cu diffusion into the silicon. The process of Ni electroless plating on front silicon surface is performed using a chemical bath. Additives and buffer agents such as ammonium chloride is added to maintain the stability and pH control of the bath. Ni deposition rate is found to vary with temperature, time, utilization of bath. The experimental result shown that Ni layer by SEM (scanning electron microscopy) and EDX analysis. Finally, plated Ni/Cu contact solar cell result in an efficiency of 17.69% on $2{\times}2\;cm^2$, Cz wafer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.20-23
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing(CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical polishing(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commercial slurries pads, and post-CMP cleaning alternatives are discuss, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper deposition is a mature process from a historical point of view, but a very young process from a CMP perspective. While copper electro deposition has been used and studied for decades, its application to Cu damascene wafer processing is only now gaining complete acceptance in the semiconductor industry. The polishing mechanism of Cu-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper passivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.84-87
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• 2003

Since Pb-free solder alloys have been used extensively in microelectronic packaging industry, the interaction between UBM (Under Bump Metallurgy) and solder is a critical issue because IMC (Intermetallic Compound) at the interface is critical for the adhesion of mechanical and the electrical contact for flip chip bonding. IMC growth must be fast during the reflow process to form stable IMC. Too fast IMC growth, however, is undesirable because it causes the dewetting of UBM and the unstable mechanical stability of thick IMC. UP to now. Ni and Cu are the most popular UBMs because electroplating is lower cost process than thin film deposition in vacuum for Al/Ni(V)/Cu or phased Cr-Cu. The consumption rate and the growth rate of IMC on Ni are lower than those of Cu. In contrast, the wetting of solder bumps on Cu is better than Ni. In addition, the residual stress of Cu is lower than that of Ni. Therefore, the alloy of Cu and Ni could be used as optimum UBM with both advantages of Ni and Cu. In this paper, the interfacial reactions of Sn-3.5Ag-0.7Cu solder on Ni-xCu alloy UBMs were investigated. The UBMs of Ni-Cu alloy were made on Si wafer. Thin Cr film and Cu film were used as adhesion layer and electroplating seed layer, respectively. And then, the solderable layer, Ni-Cu alloy, was deposited on the seed layer by electroplating. The UBM consumption rate and intermetallic growth on Ni-Cu alloy were studied as a function of time and Cu contents. And the IMCs between solder and UBM were analyzed with SEM, EDS, and TEM.