• Journal of the Microelectronics and Packaging Society
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• v.20 no.1
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• pp.7-13
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• 2013

3D stacked IC is one of the promising candidates which can keep Moore's law valid for next decades. IC can be stacked through various bonding technologies and they were reviewed in this report, for example, wafer direct bonding and atomic diffusion bonding, etc. As an effort to reduce the high temperature and pressure which were required for high bonding strength in conventional Cu-Cu thermo-compression bonding, surface activated bonding, solid liquid inter-diffusion and direct bonding interface technologies are actively being developed.

• Korean Journal of Materials Research
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• v.16 no.2
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• pp.80-84
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• 2006

The removal efficiency of Cu and Fe contaminants on the silicon wafer surface was examined to investigate the effect of cleaning solutions on the behavior of metallic impurities. Silicon wafers were intentionally contaminated with Cu and Fe solutions by spin coating and cleaned in different types of cleaning solutions based on $NH_4OH/H_2O_2/H_2O\;(SC1),\;H_2O_2/HCl/H_2O$ (SC2), and/or HCl/$H_2O$ (m-SC2) mixtures. The concentration of metallic contaminants on the silicon wafer surface before and after cleaning was analyzed by vapor phase decomposition/inductively coupled plasma-mass spectrometry (VPD/ICP-MS). Cu ions were effectively removed both in alkali (SC1) and in acid (SC2) based solutions. When $H_2O_2$ was not added to SC2 solution like m-SC2, the removal efficiency of Cu impurities was decreased drastically. The efficiency of Cu ions in SC1 was not changed by increasing cleaning temperature. Fe ions were soluble only in acid solution like SC2 or m-SC2 solution. The removal efficiencies of Fe ions in acid solutions were enhanced by increasing cleaning temperature. It is found that the behavior of metallic contaminants as Cu and Fe from silicon surfaces in cleaning solutions could be explained in terms of Pourbaix diagram.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.364-365
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• 2005

This paper report nanotribological behavior between Si tip and Cu wafer surfaces which was treated various concentration of $H_2O_2$. This experimental approach has proven atomic level insight into Cu CMP. It has been used to study interfacial friction and adhesion force between Si tip and Cu wafer surfaces in air by atomic force microscopy (AFM). Adhesion force of Cu surfaces which was pre-cleaned in diluted HF solution was lager than Cu oxide surfaces. Adhesion force of Cu oxide surface was saturated around 7 nN. Slope of normal force vs lateral signal was increased as increasing concentration of $H_2O_2$ and it was saturated around 24. Friction force of Cu oxide was lager than Cu.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.10
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• pp.1023-1028
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• 2009

Cleaning is required following CMP (chemical mechanical planarization) to remove particles. The minimization of particle residue is required with each successive technology generation, and the cleaning of wafers becomes more complicated. In copper damascene process for interconnection structure, it utilizes 2-step CMP consists of Cu and barrier CMP. Such a 2-steps CMP process leaves a lot of abrasive particles on the wafer surface, cleaning is required to remove abrasive particles. In this study, the chemical mechanical cleaning(CMC) is performed various conditions as a cleaning process. The CMC process combined mechanical cleaning by friction between a wafer and a pad and chemical cleaning by CMC solution consists of tetramethyl ammonium hydroxide (TMAH) / benzotriazole (BTA). This paper studies the removal of abrasive on the Cu wafer and the cleaning efficiency of CMC process.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.215-215
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• 2012

Sillicon Wafer는 순도 99.9999999%의 단결정 규소를 사용하여 만들어진다. 웨이퍼의 표면은 결함이나 오염이 없어야 하고 회로의 정밀도에 영향을 미치기 때문에 고도의 평탄도와 정밀도를 요구한다. 특히 실리콘의 순도는 효율성에 영향을 주는 주요 원인으로 금속의 오염은 실리콘 웨이퍼의 수명을 단축시켜 효율성을 떨어뜨린다. 표면에 흡착된 구리와 니켈은 Silicon 오염의 주요인 중 하나로 알려져 있다. 이 연구는 Silicon Wafer 표면에 흡착된 구리가 내부로 확산되는 메커니즘을 규명하는 것을 목표로 한다. 표면에 구리가 흡착된 상태는 AES 및 LEED로 관찰하였다. 표면에 흡착된 구리의 표면(수평)및 내부(수직)확산은 SIMS를 이용하여 연구하였다.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.47-51
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• 2013

Chemical mechanical polishing (CMP) has become one of the key processes in wafer level stacking technology for 3D stacked IC. In this study, two-step CMP process was proposed to polish $Cu/SiO_2$ hybrid bonding surface, that is, Cu CMP was followed by $SiO_2$ CMP to minimize Cu dishing. As a result, Cu dishing was reduced down to $100{\sim}200{\AA}$ after $SiO_2$ CMP and surface roughness was also improved. The bonding interface showed no noticeable dishing or interface line, implying high bonding strength.

• Journal of the Korean Applied Science and Technology
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• v.16 no.1
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• pp.33-40
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• 1999

We used Cu as a representative of metals to be directly adsorbed on the bare Si surface and studied its removal DHF, DHF-$H_2O_2$ and BHF solution. It has been found that Cu ion in DHF adheres on every Si wafer surface that we used in our study (n, p, n+, p+) especially on the n+-Si surface. The DHF-$H_2O_2$ solution is found to be effective in removing metals featuring high electronegativity such as Cu from the p-Si and n-Si wafers. Even when the DHF-$H_2O_2$ solution has Cu ions at the concentration of 1ppm, the solution is found effective in cleaning the wafer. In the case the n+-Si and p+-Si wafers, however, their surfaces get contaminated with Cu When Cu ion of 10ppb remains in the DHF-$H_2O_2$ solution. When BHF is used, Cu in BHF is more likely to contaminate the n+-Si wafer. It is also revealed that the surfactant added to BHF improve wettability onto p-Si, n-Si and p+-Si wafer surface. This effect of the surfactant, however, is not observed on the n+-Si wafer and is increased when it is immersed in the DHF-$H_2O_2$ solution for 10min. The rate of the metallic contamination on the n+-Si wafer is found to be much higher than on the other Si wafers. In order to suppress the metallic contamination on every type of Si surface below 1010atoms/cm2, the metallic concentration in ultra pure water and high-purity DHF which is employed at the final stage of the cleaning process must be lowered below the part per trillion level. The DHF-$H_2O_2$ solution, however, degrades surface roughness on the substrate with the n+ and p+ surfaces. In order to remove metallic impurities on these surfaces, there is no choice at present but to use the $NH_4OH-H_2O_2-H_2O$ and $HCl-H_2O_2-H_2O$ cleaning.

• Proceedings of the KAIS Fall Conference
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• 2004.06a
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• pp.50-53
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• 2004

본 논문에서는 Si wafer와 Cu사이의 밀착력을 증가시키기 위해 Si wafer전처리 후 plasma와 SAMs처리 방법에 의한 Cu도금의 형성에 관한 방법을 설명하였다. Si wafer를 Piranha solution과 $0.5\%$ HF처리 후 유기박막인 SAMs과 plasma를 이용하는 방법으로 wafer와 Cu층 사이의 밀착력을 증가시켰다. 도금층의 밀착력은 scratch test 로 측정하였으며, AEM을 이용해 시편에 형성된 패턴의 형태를 관찰하고 SEM과 EDS를 이용해 시편의 조직을 관찰하였다. 그 결과 Si wafer를 O2, He, SAMs를 혼합처리 했을 때 밀착성이 가장 우수하였다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.5
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• pp.458-461
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• 2004

In order to improve the adhesion properties of copper, MPS(3-mercaptopropyltrimethoxysilane) organic film were employed. The plasma pretreatment in pure He or $He/O_{2}$ mixed gas environment greatly increased adhesion force. Adhesion force was measured by scratch test with nano indenter. Microstructures and surface roughness were observed with scanning electron microscope(SEM). The characteristics of MPS layer for pretreatment were studied with flourier transform infrared spectroscope(FT-IR) and contact angle tester. The heighest adhesion was achieved in the specimen pretreated with mixed plasma and NPS coating, which was 56mN. Other specimen showed lower value by $20{\%}$ to $30{\%}$. The roughness of substrate was not affected by the bonding strength of copper plating.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2009.10a
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• pp.171-172
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• 2009

TSV(through via silicon)를 이용한 Via의 Cu 충전에서 Seed 층의 역할은 전류의 흐름을 가능하게 하는 중요한 역할을 하고 있다. Via에 각각 Ti/Au, Ti/Cu를 증착한 후 Ti/Cu가 Ti/Au를 대체 할 수 있는지를 알아보기 위해 먼저 실리콘 웨이퍼에 via를 형성하고, 형성된 via에 기능성 박막층으로 절연층(SiO2) 및 시드층을 형성하였다. 전해도금을 이용하여 Cu를 충전한 결과 Ti/Au 및 Ti/Cu를 증착한 두 시편 모두 via와 seed층 접합면에 박리 등의 결함이 없었고, via 내부 또한 void나 seam 등이 관찰되지 않고 우수하게 충전된 것을 확인할 수 있었다.