• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.440-440
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• 2009

Semiconductor nanowires offer exciting possibilities as components of solar cells and have already found applications as active elements in organic, dye-sensitized, quantum-dot sensitized, liquid-junction, and inorganic solid-state devices. Among many semiconductors, silicon is by far the dominant material used for worldwide photovoltaic energy conversion and solar cell manufacture. For silicon wire to be used for solar device, well aligned wire arrays need to be fabricated vertically or horizontally. Macroscopic silicon wire arrays suitable for photovoltaic applications have been commonly grown by the vapor-liquid-solid (VLS) process using metal catalysts such as Au, Ni, Pt, Cu. In the case, the impurity issues inside wire originated from metal catalyst are inevitable, leading to lowering the efficiency of solar cell. To escape from the problem, the wires of purity of wafer are the best for high efficiency of photovoltaic device. The fabrication of wire arrays by the electrochemical etching of silicon wafer with photolithography can solve the contamination of metal catalyst. In this presentation, we introduce silicon wire arrays by electrochemical etching method and then fabrication methods of radial p-n junction wire array solar cell and the various merits compared with conventional silicon solar cells.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).

• Tribology and Lubricants
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• v.24 no.2
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• pp.63-71
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• 2008

Friction and adhesion tests were conducted to investigate tribological characteristics of materials for MEMS/NEMS using atomic force microscope (AFM). AFM Si tips were chemically modified with a self-assembled monolayer (SAM) derived from trichlorosilane like octadecyltrichlorosilane (OTS) and (1H, 1H, 2H, 2H-perfluorooctyl) trichlorosilane (FOTS), and various materials, such as Si, Al, Au, Cu, Ti and PMMA films, were prepared for the tests. SAMs were coated on Si wafer by dipping method prior to AFM tip to determine a proper dipping time. The proper dipping time was determined from the measurements of contact angle, surface energy and thickness of the SAMs. AFM tips were then coated with SAMs by using the same coating condition. Friction and adhesion forces between the AFM Si tip modified with SAM and MEMS/NEMS materials were measured. These forces were compared to those when AFM tip was uncoated. According to the results, after coating OTS and FOTS, the friction and adhesion forces on all materials used in the tests decreased; however, the effect of SAM on the reduction of friction and adhesion forces could be changed according to counterpart materials. OTS was the most effective to reduce the friction and adhesion forces when counterpart material was Cu film. In case of FOTS, friction and adhesion forces decreased the most effectively on Au films.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.45-50
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• 2006

Copper via filling is the important factor in 3-D stacking interconnection of SiP (system in package). As the packaging density is getting higher, the size of via is getting smaller. When DC electroplating is applied, a defect-free hole cannot be obtained in a small size via hole. To prevent the defects in holes, pulse and pulse reverse current was applied in copper via filling. The holes, $20\and\;50{\mu}m$ in diameter and $100{\sim}190\;{\mu}m$ in height. The holes were prepared by DRIE method. Ta was sputtered for copper diffusion barrier followed by copper seed layer IMP sputtering. Via specimen were filled by DC, pulse and pulse-reverse current electroplating methods. The effects of additives and current types on copper deposits were investigated. Vertical and horizontal cross section of via were observed by SEM to find the defects in via. When pulse-reverse electroplating method was used, defect free via were successfully obtained.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1098-1101
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• 1995

NbTi thin films were prepared on Si wafer and Cu substrate by rf magnetron sputtering in the range of sputtering pressure $3{\times}10^{-2}$torr to $3{\times}10^{-4}$torr at room temperature. The influence of sputtering pressure and substrate type on crystallographic orientation and morphology of NbTi thin films was investigated by using X-ray diffraction(XRD) and scanning electron microscopy(SEM), respectively. And the effect of crystallographic orientation and morphology of NbTi film on electromagnetic behaviors was estimated by measuring critical current in various applied magnetic field. The film morphology changed from porous structure consisting of tapered crystallites to densely deposited film decreasing with sputtering pressure. The change of crystallographic orientation with the sputtering pressure and rf power was calculated from the texture coefficient of(002) plane based on XRD patterns. It was found that a change of texture coefficient of(002) plane increased with decreasing sputtering pressure. From observation of critical current in various applied magnetic field, we have identified that the change of critical current abruptly decrease applying with magnetic field and NbTi film produced at high sputtering pressure does not exhibit superconductivity but at low sputtering pressure shows superconductivity.

• Clean Technology
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• v.6 no.1
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• pp.79-84
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• 2000

In this study, to reduce the consumption of chemicals in cleaning processes, Si-wafers contaiminated with metallic impurities were cleaned with electrolyzed water(EW), which was generated by the electrolysis of a diluted electrolyte solution or ultra pure water(UPW). Electrolyzed water could be controlled for obtaining wide ranges of pH and ORP(oxidation-reduction potential). The pH and oxidation-reduction potential of anode water and cathode water were measured to be 4.7 and +1000mV, and 6.3 and -550mV, respectively. To analyze the amount of metallic impurities on Si-wafer surfaces, ICP-MS was introduced. Anode water was effective for Cu removal, while cathode water was more effective for Fe removal.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.371.2-371.2
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• 2016

Graphene electronics is one of the promising technologies for the next generation electronic devices due to the outstanding properties such as conductivity, high carrier mobility, mechanical, and optical properties along with extended applications using 2 dimensional heterostructures. However, large contact resistance between metal and graphene is one of the major obstacles for commercial application of graphene electronics. In order to achieve low contact resistance, numerous researches have been conducted such as gentle plasma treatment, ultraviolet ozone (UVO) treatment, annealing treatment, and one-dimensional graphene edge contact. In this report, we suggest a fabrication method of one-dimensional graphene metal edge contact without using graphene exfoliation. Graphene is grown on Cu foil by low pressure chemical vapor deposition. Then, the graphene is transferred on $SiO_2/Si$ wafer. The patterning of graphene channel and metal electrode is done by photolithography. $O_2$ plasma is applied to etch out the exposed graphene and then Ti/Au is deposited. As a result, the one-dimensional edge contact geometry is built between metal and graphene. The contact resistance of the fabricated one-dimensional metal-graphene edge contact is compared with the contact resistance of vertically stacked conventional metal-graphene contact.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2003.10a
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• pp.93-96
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• 2003

Recently, various bulk metallic glasses (BMG's) haying good mechanical and chemical properties were developed. BMG's can easily be deformed in the supercooled liquid region, via viscous flow mechanism. In our previous work, we evaluated the deformation behavior and some other basic properties of Z $r_{41.2}$ $Ti_{13.8}$C $u_{12.5}$N $i_{10}$B $e_{22.5}$ alloy. In this study, we investigated the micro forming of Z $r_{41.2}$ $Ti_{13.8}$C $u_{12.5}$N $i_{10}$B $e_{22.5}$ alloy. The process condition was chosen based on the viscosity data from TMA, and superalloy and Si wafer with micro patterns on the surface were used as forming die. The alloy showed good replication of the patterns. However, some stripe patterns, resembling scratches, appeared on the deformed alloy surface. These scratches can be reduced or eliminated by polishing before forming.ing.ore forming.ing.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2017.05a
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• pp.70-70
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• 2017

TSV(through silicon via)는 긴 종횡비를 갖는 패턴에 Cu, Ta, Ti을 높은 conformality를 갖도록 증착하는 공정이다. Magnetron cathode의 자석 배열 설계는 target 물질 종류에 따라서 multitrack, water drop type등이 있으며 target과 substrate 사이의 공간에 플라즈마를 형성시켜서 기판에 이온 입사량을 늘린 후 기판 바이어스를 이용하여 이온 충돌, re-sputtering을 통한 재증착 과정을 통해 치밀한 금속 박막을 연속적으로 형성할 수 있도록 하는 것이 목적이다. 또한 sputter가 사용되고 있는 분야에 효율을 증대시키고, 증착되는 막의 품질향상을 위해 UBMS를 사용하고 있으며, 산업에 사용되어 지는 300 mm wafer용 시스템은 제작비가 약 10억 원 정도 소요되며 다양한 테스트를 진행하기 위해선 많은 비용이 소요된다. 따라서 비용과 소요시간을 줄여 다양한 테스트를 위해 소규모 플라즈마 시스템을 설계하게 되었다. 61 l/sec 터보 분자 펌프와 다이아프램 펌프를 기초로한 TMP station에 2.75 인치 CF flange가 장착된 6 way cross를 main 챔버로 활용하고, 작은 size의 unbalanced magnetron cathode를 제작, 장착한 다음 6 way cross 주변에 전자석을 적절히 배치하여 300 mm wafer system에서와 동일한 물리적 현상을 테스트 할 수 있도록 하였다. Fig1. (a) UBMS system의 사진을 나타내었고, (b)에는 6 way cross 내부에 발생된 플라즈마의 형상을 나타내었다. 전원 장치는 Advanced Energy사의 MDX-1.5K DC power supply를 사용하였고, 방전 전압 - 전류 관계의 가스 압력에 따른 plasma 현상과 magnetron 배율에 따른 plasma 현상 그리고 전자석에 의한 영향을 주로 관찰 하였다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.179-180
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• 2012

Aluminum alloys are widely known as non-ferrous metal with light weight and high strength. Consequently, these materials take center stage in the aircraft and automobile industry. The Al7075 aluminum alloy is based on the Al-Zn-Mg-Cu and one of the strongest wrought aluminum alloys. Aluminum nitride has ten times higher thermal conductivity($319W/m{\cdot}K$) than Al2O3 and also has outstanding electric insulation($1{\times}1014{\Omega}{\cdot}cm$). Furthermore, it has high mechanical property (430 MPa) even though its co-efficient of thermal expansion is less than alumina For these reasons, it has great possibilities to be used for not only the field which needs high strength lightweight but also electronic material field because of its suitability to be applied to the insulator film of PCB or wafer of ceramic with high heat conduction. This paper investigates the mechanical properties and corrosion behavior of aluminum alloy Al7075 deposited with aluminum nitride thin films To improve the surface properties of Al7075 with respect to hardness, and resistance to corrosion, aluminum nitride thin films have been deposited by pulsed DC reactive magnetron sputtering. The pulsed DC power provides arc-free deposition of insulating films.