• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.65-74
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• 2013

The through-silicon via (TSV) technology is essential for 3-dimensional integrated packaging. TSV technology, however, is still facing several reliability issues including interfacial delamination, crack generation and Cu protrusion. These reliability issues are attributed to themo-mechanical stress mainly caused by a large CTE mismatch between Cu via and surrounding Si. In this study, the thermo-mechanical reliability of copper TSV technology is investigated using numerical analysis. Finite element analysis (FEA) was conducted to analyze three dimensional distribution of the thermal stress and strain near the TSV and the silicon wafer. Several parametric studies were conducted, including the effect of via diameter, via-to-via spacing, and via density on TSV stress. In addition, effects of annealing temperature and via size on Cu protrusion were analyzed. To improve the reliability of the Cu TSV, small diameter via and less via density with proper via-to-via spacing were desirable. To reduce Cu protrusion, smaller via and lower fabrication temperature were recommended. These simulation results will help to understand the thermo-mechanical reliability issues, and provide the design guideline of TSV structure.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2012.11a
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• pp.123-123
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• 2012

최근 연구되고 있는 TSV(Through Silicon Via) 기술은 Si 웨이퍼 상에 직접 전기적 연결 통로인 관통홀을 형성하는 방법으로 칩간 연결거리를 최소화 할 수 있으며, 부피의 감소, 연결부 단축에 따른 빠른 신호 전달을 가능하게 한다. 이러한 TSV 기술은 최근의 초경량화와 고집적화로 대표되는 전자제품의 요구를 만족시킬 수 있는 차세대 실장법으로 기대를 모으고 있다. 한편, 납땜 재료의 주 원료인 주석은 주로 반도체 소자의 제조, 반도체 칩과 기판의 접합 및 플립 칩 (Flip Chip) 제조시의 범프 형성 등 반도체용 배선재료에 널리 사용되고 있다. 최근에는 납의 유해성 때문에 대부분의 전자제품은 무연솔더를 이용하여 제조되고 있지만, 주석을 이용한 반도체 소자가 고밀도화, 고 용량화 및 미세피치(Fine Pitch)화 되고 있기 때문에, 반도체 칩의 근방에 배치된 주석으로부터 많은 알파 방사선이 방출되어 메모리 셀의 정보를 유실시키는 소프트 에러 (Soft Error)가 발생되는 위험이 많아지고 있다. 이로 인해, 반도체 소자 및 납땜 재료의 주 원료인 주석의 고순도화가 요구되고 있으며, 특히 알파 방사선의 방출이 낮은 로우알파솔더 (Low Alpha Solder)가 요구되고 있다. 이에 따라 본 연구는 4인치 실리콘 웨이퍼상에 직경 $60{\mu}m$, 깊이 $120{\mu}m$의 비아홀을 형성하고, 비아 홀 내에 기능 박막증착 및 전해도금을 이용하여 전도성 물질인 Cu를 충전한 후 직경 $80{\mu}m$의 로우알파 Sn-1.0Ag-0.5Cu 솔더를 접합 한 후, 접합부 신뢰성 평가를 수행을 위해 고속 전단시험을 실시하였다. 비아 홀 내 미세구조와 범프의 형상 및 전단시험 후 파괴모드의 분석은 FE-SEM (Field Emission Scanning Electron Microscope)을 이용하여 관찰하였다. 연구 결과 비아의 입구 막힘이나 보이드(Void)와 같은 결함 없이 Cu를 충전하였으며, 고속전단의 경우는 전단 속도가 증가할수록 취성파괴가 증가하는 경향을 보였다. 본 연구를 통하여 전해도금을 이용한 비아 홀 내 Cu의 고속 충전 및 로우알파 솔더 볼의 범프 형성이 가능하였으며, 이로 인한 전자제품의 소프트에러의 감소가 기대된다.

• Corrosion Science and Technology
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• v.9 no.6
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• pp.276-280
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• 2010

Copper(Cu) as an interconnecting metal layer can replace aluminum (Al) in IC fabrication since Cu has low electrical resistivity, showing high immunity to electromigration compared to Al. However, it is very difficult for copper to be patterned by the dry etching processes. The chemical mechanical polishing (CMP) process has been introduced and widely used as the mainstream patterning technique for Cu in the fabrication of deep submicron integrated circuits in light of its capability to reduce surface roughness. But this process leaves a large amount of residues on the wafer surface, which must be removed by the post-CMP cleaning processes. Copper corrosion is one of the critical issues for the copper metallization process. Thus, in order to understand the copper corrosion problems in post-CMP cleaning solutions and study the effects of DC biases and post-CMP cleaning solution concentrations on the Cu film, a constant voltage was supplied at various concentrations, and then the output currents were measured and recorded with time. Most of the cases, the current was steadily decreased (i.e. resistance was increased by the oxidation). In the lowest concentration case only, the current was steadily increased with the scarce fluctuations. The higher the constant supplied DC voltage values, the higher the initial output current and the saturated current values. However the time to be taken for it to be saturated was almost the same for all the DC supplied voltage values. It was indicated that the oxide formation was not dependent on the supplied voltage values and 1 V was more than enough to form the oxide. With applied voltages lower than 3 V combined with any concentration, the perforation through the oxide film rarely took place due to the insufficient driving force (voltage) and the copper oxidation ceased. However, with the voltage higher than 3 V, the copper ions were started to diffuse out through the oxide film and thus made pores to be formed on the oxide surface, causing the current to increase and a part of the exposed copper film inside the pores gets back to be oxidized and the rest of it was remained without any further oxidation, causing the current back to decrease a little bit. With increasing the applied DC bias value, the shorter time to be taken for copper ions to be diffused out through the copper oxide film. From the discussions above, it could be concluded that the oxide film was formed and grown by the copper ion diffusion first and then the reaction with any oxidant in the post-CMP cleaning solution.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.351.1-351.1
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• 2016

While conventional electronic devices have been fabricated on the rigid and brittle Si based wafer as a semiconducting substrate, future devices are increasingly finding applications where flexibility and stretchability are further integrated to enable emerging and wearable devices. To achieve high flexibility and stretchability, various approaches are investigated such as polymer based conducting composite, thin metal films on the polymer substrate, and structural modifications for stretchable electronics. In spite of many efforts, it is still a challenge to identify a solution that offers both high stretchability and superior electrical properties. In this paper, we introduce a highly stretchable entangled-mesh graphene showing a potential to address such requirements as stretchability and good electrical performance. Entangle-mesh graphene was synthesized by CVD graphene on the Cu foil. To analyze the mechanical properties of entangled-mesh graphene, endurance and stretching tester have been used.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.12 s.255
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• pp.1196-1202
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• 2006

A MEMS methanol reformer was fabricated and its performance was evaluated in the present study. Catalytic steam reforming of methanol was selected because the process had been widely applied in macro scale reformers. Conventional Cu/ZnO catalyst that was prepared by co-precipitation method to give the highest coating quality was used. The reactor structure was made by bonding three layers of glass wafers. The internal structure of the wafer was fabricated by the wet-etching process that resulted in a high aspect ratio. The internal surface of the reactor was coated by catalyst and individual wafers were fusion-bonded to form the reactor structure. The internal volume of the microfabricated reactor was $0.3cm^3$ and the reactor produced exhaust gas with hydrogen concentration at 73%. The production rate of hydrogen was 4.16 ml/hr that could generate power of 350 mW in a typical PEM fuel cell.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1881-1883
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• 2001

We manufactured a micro CPL by LlGA process, a new conceptual ultra-fine and precise forming method, using X-ray lithography process. We fabricated a BN X-ray mask having properties of good X-ray transmittance and large mechanical strength. Micro CPL was manufactured by dividing into an upper plate and a low plate. Each of plates was bonded by Ag paste screen printing. The upper plate was fabricated on glass wafer to observe flow and phase transformation of cooling solution. The lower plate was manufactured by Cu electroplating for good heat transmission. Precision of inner Parts, micro pin and micro channel, of manufactured micro CPL is under ${\pm}2{\mu}m$.

• Tribology and Lubricants
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• v.15 no.1
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• pp.90-97
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• 1999

Chemical-Mechanical Polishing (CMP) refers to a material removal process done by rubbing a work piece against a polishing pad under load in the presence of chemically active, abrasive containing slurry. CU process is a combination of chemical dissolution and mechanical action. The mechanical action of CMP involves tribology. The liquid slurry is trapped between the wafer (work piece) and pad (tooling) forming a lubricating film. For the first step to understand material removal rate of the CMP process, the lubricational analyses were done with commercial 100mm diameter silicon wafers to get nominal clearance of the slurry film, roll and pitch angle at the steady state. For this purpose, we calculate slurry pressure, resultant forces and moments at the steady state in the range of typical industrial polishing conditions.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.19-26
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• 2014

Through Silicon Via (TSV) technology is the shortest interconnection technology which is compared with conventional wire bonding interconnection technology. Recently, this technology has been also noticed for the miniaturization of electronic devices, multi-functional and high performance. The short interconnection length of TSV achieve can implement a high density and power efficiency. Among the TSV technology, TSV filling process is important technology because the cost of TSV technology is depended on the filling process time and reliability. Various filling methods have been developed like as Cu electroplating method, molten solder insert method and Ti/W deposition method. In this paper, various TSV filling methods were introduced and each filling materials were discussed.

• Transactions on Electrical and Electronic Materials
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• v.7 no.2
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• pp.62-66
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• 2006

Advanced CMP conditioner design requires investigations of key conditioner manufacturing parameters and their effects on pad surface and then wafer performance. In the present investigation, diamond shape, concentration, distribution, and other key manufacturing parameters are considered to improve CMP process stability and conditioner life. Self avoiding random distribution ($SARD^{TM}$) of diamond abrasives has been developed and both numerical simulation and experimental results show very stable and reliable polishing performance.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.2
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• pp.52-59
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• 2023

The effects of dielectric curing temperature and temperature/humidity treatment conditions on the interfacial adhesion energies between Ti diffusion barrier/polybenzoxazole (PBO) dielectric layers were systematically investigated for Cu redistribution layer applications of fan-out wafer level package. The initial interfacial adhesion energies were 16.63, 25.95, 16.58 J/m² for PBO curing temperatures at 175, 200, and 225 ℃, respectively. X-ray photoelectron spectroscopy analysis showed that there exists a good correlation between the interfacial adhesion energy and the C-O peak area fractions at PBO delaminated surfaces. And the interfacial adhesion energies of samples cured at 200 ℃ decreased to 3.99 J/m² after 500 h at 85 ℃/85 % relative humidity, possibly due to the weak boundary layer formation inside PBO near Ti/PBO interface.