• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 The IMAPS-Korea Workshop 2001 Emerging Technology on packaging
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• pp.119-126
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• 2001

Chip-on-glass(COG) mounting of area array electronic packages was attempted by heating the rear surface of a contact pad film deposited on a glass substrate. The pads consisted of an adhesion(i.e. Cr or Ti) and a top coating layer(i.e. Ni or Cu) was heated by an UV laser beam transmitted through the glass substrate. The laser energy absorbed on the pad raised the temperature of a solder ball which is in physical contact with the pad, forming a reflowed solder bump. The effects of the adhesion and top coating layer on the laser reflow soldering were studied by measuring temperature profile of the ball during the laser heating process. The results were discussed based on the measurement of reflectivity of the adhesion layer. In addition, the microstructures of solder bumps and their mechanical properties were examined.

• Journal of Welding and Joining
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• 제25권2호
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• pp.76-81
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• 2007

Solder bumps have been used to interconnect the chip and substrate, and the size of the solder bump decreases below $100{\mu}m$ to accommodate higher packaging density. In order to fabricate solder bumps, a mold to chip transfer process is suggested in this work. Since the thin stainless steel mold is not wet by the solder, the molten solder is forced to fill the mold cavities with ultrasonic vibration. The solders within the mold cavities are transferred to the Cu pads on the polyimide film through reflow soldering.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2002년도 Proceedings of the International Welding/Joining Conference-Korea
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• pp.463-468
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• 2002

This study investigates the variations of shear force, displacement, and fracture surface with the shear speed and the number of reflows. The experimental data of shear tests indicate that the shear force increases as increasing the number of reflows and the shear speed due to the formation of a kind of intermetallic compound, Ni$_3$Sn$_4$, on Au/Ni/Cu pad, and the work-hardening. However, general trends show that the shear force decreases due to increasing the thickness of the intermetallic compound over 4x reflow. It is observed that the intermetallic compound which is formed between solder and pad increases according to increasing the number of reflows, and the growth rate of the intermetallic compound at central region on the interface is faster than one at edge part. The general tendencies of shear force and displacement with different shear speeds are almost identical as an increase of the number of reflows.

• Journal of Welding and Joining
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• 제18권6호
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• pp.74-82
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• 2000

The fluxless wetting properties of UBM-coated Si-wafer to the binary lead-free solders(Sn-Ag, Sn-Sb, Sjn-In, Sn0Bi) were estimated by wetting balance method. With the new wettability indices from the wetting curves of one side coated specimen, the wetting property estimation of UBM-coated Si-wafer was possible. For UBM of Si-chip, Au/Cu/Cr UBm was better than au/Ni/TI in the point of wetting time/ At general reflow process temperature, the wettability of high melting point solders(Sn-Sb, Sn-Ag) was better than that of low melting point one(Sn-Bi, Sn-In). The contact angle of the one side coated Si-plate to the solder could be calculated from the force balance equation by measuring the static state force and the tilt angle.

• ETRI Journal
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• 제35권2호
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• pp.340-343
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• 2013

A novel bumping process using solder bump maker is developed for the maskless low-volume solder on pad (SoP) technology of fine-pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low-volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low-volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of $130{\mu}m$ is successfully formed.

• 마이크로전자및패키징학회지
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• 제24권1호
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• pp.45-50
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• 2017

본 연구에서는 Sn-0.7Cu-xZn 무연솔더와 OSP 표면처리 된 솔더접합부의 전단강도를 Zn 함유량에 따라 평가하였다. 다섯 종류의 Sn-0.7Cu-xZn (x=0, 0.5, 1.0, 1.5, 2.0 wt.%) 솔더페이스트를 제작한 뒤, OSP(organic solderability preservative) 표면처리 한 PCB(printed circuit board) 기판의 전극에 리플로우 공정으로 180 um 직경의 솔더볼을 형성하였다. 전단강도는 두 가지 조건의 전단속도(0.01, 0.1 m/s)로 고속전단시험(high speed shear test)을 통해 측정하였고, 고속전단시험 시에 측정된 F-x(Force-distance) curve를 통해 파괴에너지(fracture energy)를 계산하였다, SEM(주사전자현미경, scanning electron microscopy)과 EDS(energy dispersive spectroscopy) 분석을 통하여 단면과 파단면을 관찰하였고, 금속간 화합물(intermetallic compound, IMC) 층을 분석하였다. Zn 함유량이 증가함에 따라 금속간 화합물 층의 두께는 감소하였고, Zn 함유량이 0.5 wt.%일 때 가장 높은 전단 강도(shear strength)를 나타내었다. 전체적으로 높은 전단속도 조건의 전단강도 값이 낮은 전단속도 조건의 전단강도보다 높았다.

• 마이크로전자및패키징학회지
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• 제12권4호통권37호
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• pp.289-299
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• 2005

실험과 비선형 유한요소해석을 병행하여, area array 패키지에서 솔더 접합부 특성을 판별하기 위한 전단시험 결과에 미치는 전단속도와 높이의 영향을 연구하였다. 전단속도의 증가와 전단높이의 감소에 따라 전단강도는 증가하는 경향을 나타내었다. 과대하게 높은 전단높이는 비정상적으로 높은 표준편차 또는 솔더볼 표면으로부터 전단 프로브의 밀림 현상과 같은 실험오차를 발생시켰다. 반면, 낮은 전단 속도는 취약한 계면 파괴나 계면에서 가장 약한 층의 판별에 있어서 유용하였다. 한편, 리플로우 회수 증가에 따른 Sn-37Pb/Cu와 Sn-3.5Ag/Cu BGA 솔더 접합부의 기계적${\cdot}$전기적 특성에 대하여 연구하였다. Cu6Sn5와 Cu3Sn으로 구성된 금속간화합물 층의 총 두께는 리플오우 시간의 1/3승에 비례하여 증가하였다. 전단 강도는 3회 또는 4회 리플로우까지 증가한 후, 이후 리플로우 회수에 비례하여 감소하는 경향을 나타내었다. 이때, 파괴는 리플로우 회수에 관계없이 솔더 내에서 발생하였다. 진기 비저항은 리플로우 회수에 비례하여 증가하였다.

• 한국재료학회지
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• 제18권1호
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• pp.38-44
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• 2008

The micro-structural changes, strength characteristics, and micro-fractural behaviors at the joint interface between a Sn-4.0wt%Ag-0.5wt%Cu solder ball and UBM treated by isothermal aging are reported. From the reflow process for the joint interface, a small amount of intermetallic compound was formed. With an increase in the isothermal aging time, the type and amount of the intermetallic compound changed. The interface without an isothermal treatment showed a ductile fracture. However, with an increase in the aging time, a brittle fracture occurred on the interface due mainly to the increase in the size of the intermetallic compounds and voids. As a result, a drastic degradation in the shear strength was observed. From a microshear test by a scanning electron microscope, the generation of micro-cracks was initiated from the voids at the joint interface. They propagated along the same interface, resulting in coalescence with neighboring cracks into larger cracks. With an increase in the aging time, the generation of the micro-structural cracks was enhanced and the degree of propagation also accelerated.

• 한국전기전자재료학회논문지
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• 제32권1호
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• pp.6-12
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• 2019

Bonding properties of epoxy-containing solder joints were investigated by a high temperature aging test. Specimens were prepared by bonding an R3216 standard chip resistor to an OSP-finished PCB by a reflow process with two basic types of solder (SAC305 & Sn58Bi) pastes and two epoxy-solder (SAC305+epoxy & Sn58Bi+epoxy) pastes. In all epoxy solder joints, an epoxy fillet was formed in the hardened epoxy, lying around the outer edge of the solder joint, between the chip and the Cu pad. In order to analyze the bonding characteristics of solder joints at high temperatures, a high-temperature aging test at $150^{\circ}C$ was carried out for 14 days (336 h). After aging, the intermetallic compound $Cu_6Sn_5$ was found to have formed in the solder joint on the Cu pad, and the shear stress on the conventional solder joint was reduced by a significant amount. The reason that the shear force did not decrease much, even though in epoxy solder, was thatbecause epoxy hardened at the outer edge of the supported solder joints. Using epoxy solder, strong bonding behavior can be ensured due to this resistance to shear force, even in metallurgical changes such as those where intermetallic compounds form at solder joints.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.102-102
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• 2018

Electronic industry had required the finer size and the higher performance of the device. Therefore, 3-D die stacking technology such as TSV (through silicon via) and micro-bump had been used. Moreover, by the development of the 3-D die stacking technology, 3-D structure such as chip to chip (c2c) and chip to wafer (c2w) had become practicable. These technologies led to the appearance of HBM (high bandwidth memory). HBM was type of the memory, which is composed of several stacked layers of the memory chips. Each memory chips were connected by TSV and micro-bump. Thus, HBM had lower RC delay and higher performance of data processing than the conventional memory. Moreover, due to the development of the IT industry such as, AI (artificial intelligence), IOT (internet of things), and VR (virtual reality), the lower pitch size and the higher density were required to micro-electronics. Particularly, to obtain the fine pitch, some of the method such as copper pillar, nickel diffusion barrier, and tin-silver or tin-silver-copper based bump had been utillized. TCB (thermal compression bonding) and reflow process (thermal aging) were conventional method to bond between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degrees. However, because of tin overflow which caused by higher operating temperature than melting point of Tin ($232^{\circ}C$), there would be the danger of bump bridge failure in fine-pitch bonding. Furthermore, regulating the phase of IMC (intermetallic compound) which was located between nickel diffusion barrier and bump, had a lot of problems. For example, an excess of kirkendall void which provides site of brittle fracture occurs at IMC layer after reflow process. The essential solution to reduce the difficulty of bump bonding process is copper to copper direct bonding below $300^{\circ}C$. In this study, in order to improve the problem of bump bonding process, copper to copper direct bonding was performed below $300^{\circ}C$. The driving force of bonding was the self-annealing properties of electrodeposited Cu with high defect density. The self-annealing property originated in high defect density and non-equilibrium grain boundaries at the triple junction. The electrodeposited Cu at high current density and low bath temperature was fabricated by electroplating on copper deposited silicon wafer. The copper-copper bonding experiments was conducted using thermal pressing machine. The condition of investigation such as thermal parameter and pressure parameter were varied to acquire proper bonded specimens. The bonded interface was characterized by SEM (scanning electron microscope) and OM (optical microscope). The density of grain boundary and defects were examined by TEM (transmission electron microscopy).