• The Transactions of the Korean Institute of Electrical Engineers P
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• v.62 no.2
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• pp.98-102
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• 2013

There are so many CCTV in our streets, buildings and public places. Nevertheless, security methods for CCTV are rarely. This paper describes a study on developing a media crypto algorithm for anti-hacking into CCTV. H.264 codec is used to compress the video stream in CCTV systems. HIGHT algorithm provided by KISA is adopted as a crypto algorithm in our development. Other crypto methods except HIGHT could be selected by company's security police. Only some bytes in VCL(Video Coding Layer) of H.264 are encrypted to improve the performance of limited platforms, such as CCTV, WebCam, smartphone. Very fast and light crypto algorithm was developed by our researches.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.1014-1017
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• 2003

In this paper, after the crypto acceleration board of the server-termination type is designed, we implement the Elliptic Curve Digital Signature Algorithm on the board that serves data integrity and user authentication. For implementing ECDSA, we use crypto co-processor, MPC180, to reduce the computation burden of main Processor (MPC860) on the board. By using crypto co-processor, the computation efficiency in case prime field is improved more between 90 and 100 times than the software library and between 20 and 90 times in case binary field. Our result is expect to apply for SSL acceleration board.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.46 no.7
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• pp.602-609
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• 2018

This paper proposes the hybrid crypto-system for fast video data encryption of UAV(Unmanned Aerial Vehicle) under the LTE(Long-Term Evolution) wireless communication environment. This hybrid crypto-system is consisted of ECC(Elliptic Curve Cryptography) public key algorithm and LEA(Light-weight Encryption Algorithm) symmetric key algorithm. ECC is a faster public key algorithm with the same security strength than RSA(Rivest Shamir Adleman), and Korean standard LEA with the same key size is also a faster symmetric key algorithm than AES(Advances Encryption Standard). We have implemented this hybrid crypto-system using OpenSSL, OpenCV and Socket programs under the Swarm 8-UAV. We have shown the efficient adaptability of this hybrid crypto-system for the real-time swarm UAV through the experiments under the LTE communication environment.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.164-167
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• 2002

This paper presents the design of Rijndael crypto-processor with 128 bits, 192 bits and 256 bits key size. In October 2000 Rijndael cryptographic algorithm is selected as AES(Advanced Encryption Standard) by NIST(National Institute of Standards and Technology). Rijndael algorithm is strong in any known attacks. And it can be efficiently implemented in both hardware and software. We implement Rijndael algorithm in hardware, because hardware implementation gives more fast encryptioN/decryption speed and more physically secure. We implemented Rijndael algorithm for 128 bits, 192 bits and 256 bits key size with VHDL, synthesized with Synopsys, and simulated with ModelSim. This crypto-processor is implemented using on-the-fly key generation method and using lookup table for S-box/SI-box. And the order of Inverse Shift Row operation and Inverse Substitution operation is exchanged in decryption round operation of Rijndael algorithm. It brings about decrease of the total gate count. Crypto-processor implemented in these methods is applied to mobile systems and smart cards, because it has moderate gate count and high speed.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.437-440
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• 2001

암호 알고리즘을 디지털 통신에 적용하기 위해서는 고속 처리가 필수적이며, 고속화를 위하여 암호 칩으로 구현하고 있다. 프롬투정보통신에서는 암호칩을 효과적으로 제작하기 위하여 MPC 850 프로세서와 FPGA를 내장하고 통신 포트를 사용할 수 있게 하는 암호툴인 CryptoModule 2000을 발표하였다. 이 논문에서는 CryptoModule 2000을 이용하여 3GPP에서 적용하고 있는 KASUMI 암호 알고리즘을 구현하고 시험 결과를 분석하여 CryptoModule 2000이 암호 시스템 개발용으로 적합함을 확인한다.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.271-276
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• 2019

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.447-457
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• 2004

This paper proposes a RSA crypto-processor for embedded systems. The architecture of the RSA crypto-processor should be used relying on Big Montgomery algorithm, and is supported by configurable bit size. The RSA crypto-processor includes a RSA control signal generator, an optimal Big Montgomery processor(adder, multiplier). We use diverse arithmetic unit (adder, multiplier) algorithm. After we compared the various results, we selected the optimal arithmetic unit which can be connected with ARM core-processor. The RSA crypto-processor was implemented with Verilog HDL with top-down methodology, and it was verified by C language and Cadence Verilog-XL. The verified models were synthesized with a Hynix 0.25${\mu}{\textrm}{m}$, CMOS standard cell library while using Synopsys Design Compiler. The RSA crypto-processor can operate at a clock speed of 51 MHz in this worst case conditions of 2.7V, 10$0^{\circ}C$ and has about 36,639 gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.9
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• pp.851-858
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• 2012

Java crypto library such as SUN JCA/JCE or BC JCE is generally used to implement secure applications for smart devices using Android platform. Programming functions written by Java language are launched and executed inside Java Virtual Machine (JVM), thereby difficult to use system hardware specific functionalities and degrading performance as well. In case of crypto primitive, few secure applications can use crypto primitive executing in JVM because both amount of computing and complexity of such primitives are very high. From the aspect of performance, in particular, time sensitive real time applications such as streaming services or secure application frequently applying public key based crypto algorithm cannot use Java crypto library. To solve the problem, we design and implement crypto library which employ JNI and NDK methods to directly access functions that implemented by native language such as C or C++. The proposed Java Crypto provider supports faster execution. Also developer can use our provider in the same way by writing traditional Java crypto library.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.584-586
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• 2017

In this paper we provide a unified crypto core that integrates lightweight symmetric cryptography and authentication. The crypto core implements a unified 128 bit key architecture of PRESENT encryption algorithm and a new lightweight encryption algorithm. The crypto core also consist of an authentication unit which neglects the use of hashing algorithms. Four algorithms are used for authentication which come from the Hopper-Blum (HB) and Hopper-Blum-Munilla-Penado (HB-MP) family of lightweight authentication algorithms: HB, HB+, HB-MP and HB-MP+. A unified architecture of these algorithms is implemented in this paper. The unified cryptosystem is designed using Verilog HDL, simulated with Modelsim SE and synthesized with Xilinx Design Suite 14.3. The crypto core synthesized to 1130 slices at 189Mhz frequency on Spartan6 FPGA device.

• Proceedings of the IEEK Conference
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• 2001.06c
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• pp.55-58
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• 2001

In this paper, we present the development of a JavaCard for public key crypto algorithms and its performance evaluation. To make a high performance for the public key crypto algorithm such as RSA and ECC on a JavaCard, we have implemented a crypto coprocessor in hardware and ported it to the card operating system and virtual machine environments. The performance of the public key crypto algorithms on the JavaCard shows that our JavaCard is suitable for If card applications which needs high performance and high level of security.