• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1816-1819
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• 2003

As a result of milling operation, we expect to have burr at the outward edge of workpiece. Also, it causes undesirable problems such as deburring cost, low quality of machined surface, and bottleneck in manufacturing process. Though it is impossible to totally remove burr in machining, it is necessary to plan a machining process that minimizes the occurrence of burr. In this paper, a scheme is proposed which identifies the tool path of the milling operation with minimum burr. In the previous research, a Burr Expert System was developed where the feature identification, the cutting condition identification, and the analysis on exit burr formation are the key steps in the program. The Burr Expert System predicts which portion of workpiece would have the exit burr in advance so that we can calculate the burr length of each milling operation. Here, the critical angle determines whether the burr analyzed is an exit burr or not. So the burr minimization scheme becomes to minimize the burr with critical angle. By iterating all the possible tool paths in certain milling operation, we can identify the tool path with minimum burr.

• ETRI Journal
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• v.26 no.6
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• pp.545-554
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• 2004

In this paper, we propose an efficient design method for area optimization in a digital filter. The conventional methods to reduce the number of adders in a filter have the problem of a long critical path delay caused by the deep logic depth of the filter due to adder sharing. Furthermore, there is such a disadvantage that they use the transposed direct form (TDF) filter which needs more registers than those of the direct form (DF) filter. In this paper, we present a hybrid structure of a TDF and DF based on the flattened coefficients method so that it can reduce the number of flip-flops and full-adders without additional critical path delay. We also propose a resource sharing method and sharing-pattern searching algorithm to reduce the number of adders without deepening the logic depth. Simulation results show that the proposed structure can save the number of adders and registers by 22 and 26%, respectively, compared to the best one used in the past.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1259-1265
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• 2006

In this paper, we propose a combined synthetic algorithm of the logic level for high speed FPGA design. The algorithm divides critical path to reduce delay time and generates a circuit which the divided circuits execute simultaneously. This kernel selection algorithm is made by C-langage of SUN UNIX. We compare this with the existing FlowMap algorithm. This proposed algorithm shows result on 33.3% reduction of delay time by comparison with the existing algorithm.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.3
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• pp.197-203
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• 2009

Finite field arithmetic is very important in the area of cryptographic applications and coding theory, and it is efficient to use normal bases in hardware implementation. Using the fact that $GF(2^{mk})$ having a type-I optimal normal basis becomes the extension field of $GF(2^m)$, we, in this paper, propose a new serial multiplier which reduce the critical XOR path delay of the best known Reyhani-Masoleh and Hasan's serial multiplier by 25% and the number of XOR gates of Kwon et al.'s multiplier by 2 based on the Reyhani-Masoleh and Hasan's serial multiplier for type-I optimal normal basis.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.823-826
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• 2003

FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.7
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• pp.734-745
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• 1988

In this paper, it is tried to improve efficiency of the D-algorithm by assigning the logic values effectively on the nodes related to the critical path for back tracing to reduce the number of search nodes when acyclic combinational logic circuits are composed of NAND gates only. For that purpose, LASAR algorithm which is suitable for determining a critical path for back tracing is applied to the D-algorithm and it is implemented by IBM-PC with APL language. The test results on a number of NAND circuits which have multi-fanout, reconvergent and symetric characteristics show that the modified D-algorihtm reduces the number of search nodes in forward and backward tracing and decreases the run time of CPU about 10 percents.

• Journal of Construction Engineering and Project Management
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• v.3 no.2
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• pp.21-34
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• 2013

Various risk factors affect construction projects. Due to the uncertainties created by risk factors, actual activity durations frequently deviate from the estimated durations in either favorable or adverse direction. For this reason, evaluation of schedule uncertainty is required to make decisions accurately when managing construction projects. In this regard, this paper presents a new computer simulation model - the Repetitive Schedule Risk Analysis Model (RSRAM) - to evaluate unit-based repetitive building project schedules under uncertainty when activity durations and risk factors are correlated. The proposed model utilizes Monte Carlo Simulation and a Critical Path Method based repetitive scheduling procedure. This new procedure concurrently provides the utilization of resources without interruption and the maintenance of network logic through successive units. Furthermore, it enables assigning variable production rates to the activities from one unit to another and any kind of relationship type with or without lag time. Details of the model are described and an example application is presented. The findings show that the model produces realistic results regarding the extent of uncertainty inherent in the schedule.

• Proceedings of the Korean Society of Agricultural Engineers Conference
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• 1999.10c
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• pp.575-581
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• 1999

Yielding is an important feature of the stress-strain behavior of clays. This study was performed to estabilish the yielding curves and properties for a marine caly from Jangheung. Chonnam Province . A series of tests was done by means of the various stress path tests. Results of the tests are as follows ; 1) The laboratory -determined Ko is very similar to that applied to the Jaky equation. 2) The shape of yielding curve is nealry symmetrical about the p' axis like other natural clays. 3) The critical state parameters, Mc and Me are the same for compression and extension tests which contrasts with the results of the isotropically consolidated soils. 4) The state boundary suface using the critical state paratmers can resresent the normalized yielding curve obtained by various stress path experiments.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.310-313
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• 2000

This paper presents a new scheduling method for ILP processing called NHS(Novel Hybrid Scheduling). It concerns not only exploiting as much ILP as possible like other state-of-the-art scheduling scheme, but also choosing the most important instructions among many ready-to-execute instructions to processors in order to reduce the execution time under limited hardware resource. At the heart of NHS is a conception called CCP(Complex Critical Path), an extension of CP(Critical Path). By using CCP, compiler not only can get a global information of the whole program to extract ILP, but also can collecting data dependence information and control flow information. The paper also presents the simulation results, to date, of our attempts to study the NHS scheduling method. The results indicate good potential for this scheduling method.

• International conference on construction engineering and project management
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• 2007.03a
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• pp.520-529
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• 2007

Apportioning responsibilities of concurrent delay to the owner and the contractor is a difficult task, due to the sophisticate nature both in the schedule and in the factors that cause the delay. This research attempts to develop a simplified yet systematic approach that can be used for a fair apportionment of concurrent delay. A concurrent delay is defined herein as when the contractor and the owner have both caused independent critical path delays during the same approximate time period. Incorporating the concepts of windows analysis and critical path method (CPM), the developed approach has three "windowing of delay" steps to quickly apportion the delay in each of these windows, and a fourth step to sum up those apportioned delays to obtain each party's final responsibilities. This developed approach is found to be simple and effective at this stage; it will be tested against real cases in the near future.