• Journal of the Korean Society of Clothing and Textiles
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• v.16 no.4 s.44
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• pp.443-455
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• 1992

The purpose of this study is to verify the theoretical model on the clothing satisfaction. Research problems are as following; 1. To identify a causal model on the clothing satisfaction. 2. To examine the causal model by the brand levels. 3. To examine the causal model by the consumer characteristics. The empirical study of the above research problems is carried out by the longitudinal survey. The subjects selected for the final analysis are 362 women living in Seoul and Pusan. The results of our analysis are as following; 1. The main causal course of the clothing satisfaction is that the brand level and the consumer expectation $\rightarrow$ the expectation $\rightarrow$ the perceived performance ($\rightarrow$ the disconfirmation) $\rightarrow$ the clothing satisfaction. Those relevant variables explain $70\%$ of the clothing satisfac-tion variance. Especially, the influence of the perceived performance appears to be greater than that of the disconfirmation. 2. According to our analysis, the expectation influences the clothing satisfaction indirectly through the perceived performance. Especially, the normative expectation exhibits the contrast effect on the disconfirmation, while the predictive expectation exhibits the assimilation effect on the perceived performance. 3. The clothing satisfaction model differs by the brand levels (high price brand vs. moderate price brand) and by the consumer involvement levels (high involvement vs. low involvement). The relevant variables explain $65\%$ of the clothing satisfaction variance in the high price brand, while they explain $77\%$ in the moderate price brand. In the high involvement group, the relevant variables explain $78\%$ of the clothing satisfaction variance and $60\%$ in the low involvement group. In both involvement groups, the most critical direct variable is the perceived perfor-mance. In conclusion, we find that the clothing satisfaction can be explained by three constructs, the expectation, the perceived performance and the disconfirmation. The hypothesis that the two dimensions of the expectation explain the clothing satisfaction better is empirically supported in our study. Finally, we find that the clothing satisfaction models differ between two brand levels and consumer involvement levels.

• Progress in Superconductivity
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• v.7 no.2
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• pp.114-119
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• 2006

High critical current density, high n value, multiple faults endurances, and fast recovery characteristics of YBCO thin films are very attractive characteristics for developing resistive type superconducting fault current limiters. But due to the limited current and voltage ratings of one YBCO module, it is needed to construct series and parallel module connections for high capacity electric networks. Especially for distribution network, more than 30 units should be connected in series to meet voltage level. So in order to construct distribution-level superconducting fault current limiter, simultaneous quench in one YBCO thin films should be realized, and furthermore, quench should be occurred in all fault current limiting units equally to avoid local heating and failures. In this paper, we proposed optimum design of YBCO thin films for fault current limiting module and technical method using shunt resistor to achieve simultaneous quench between multi current limiting units. From the analytical and the experimental results, optimal current path and thickness of shunt material was determined for YBCO thin films and shunt resistor between modules was developed. Finally, 14 kV one phase resistive fault current limiter using multi YBCO thin films was constructed and it was possible to get satisfactory test results.

• Journal of Internet Computing and Services
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• v.15 no.5
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• pp.1-7
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• 2014

WireWireless sensor networks(WSNs) are generally comprised of densely deployed sensor nodes, which causes highly redundant sensor data transmission and energy waste. Many studies have focused on energy saving in WSNs. However, delay problem also should be taken into consideration for mission-critical applications. In this paper, we propose a BISA (Bio-Inspired Scheduling Algorithm) to reduce the energy consumption and delay for WSNs inspired by biological systems. BISA investigates energy-efficient routing path and minimizes the energy consumption and delay using multi-channel for data transmission. Through simulations, we observe that the BISA archives energy efficiency and delay guarantees.

• Korean Journal of Construction Engineering and Management
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• v.10 no.2
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• pp.26-33
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• 2009

The required level of detail in scheduling depends on the stages in the construction life-cycle. The objective of this study is to provide a Standardized Schedule Model (SSM) with an aim to facilitate the estimating of construction duration in the planning stage. The SSM modularizes work items; establishes relations between preceding and succeeding activities; and calculates approximate construction duration. The estimated duration of the SSM was compared with the detailed duration from the commercial scheduling tool using actual work activities. The difference showed to be ranged between -3.1% and +15%, which demonstrates that the SSM can be feasibly applied to the approximate estimation of construction duration.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.331-336
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• 2004

This study focuses on the hardware implementation of fast and low-system-complexity multiplier over GF(2$^{m}$ ). From the properties of an irreducible AOP of degree m. the modular reduction in GF(2$^{m}$ ) multiplicative operation can be simplified using cyclic shift operation. And then, GF(2$^{m}$ ) multiplicative operation can be established using the away structure of AND and XOR gates. The proposed multiplier is composed of m(m+1) 2-input AND gates and (m+1)$^2$ 2-input XOR gates. And the minimum critical path delay is Τ$_{A+}$〔lo $g_2$$^{m}$ 〕Τ$_{x}$ proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.n.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.276-287
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• 2004

An ad hoc network is infra(Base Sstation or Access Point) free wireless mobile communication technology. Mobile nodes function as routers and servers in ad hoc networks. Many routing protocols for ad hoc network have been proposed. If any route is broken owing to moving node, source must repair broken route again. But route repair technology after route collapses is not suitable to transmit real-time data packet for QoS guarantee. So this paper presents route repair technology that prevents route from breaking. If intermediate node moves to critical section, the node issues handoff packet and sends the packet to the next node. After next node receives handoff packet, the node broadcasts route request packet to the previous node for intermediate node. Finally, even if intermediate node moves out of the routing region, the source can continuously transmit data packets to the destination through the new path.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• Korean journal of communication and information
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• v.66
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• pp.273-297
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• 2014

This paper conducted a survey targeting online Korean drama viewers in Vietnam and Philippines, to investigate the relationships between viewing motivations of Korean drama, general attitude toward Korean drama, and Korea's national image. Factor analyses found six viewing motivations of Korean drama, and the most powerful viewing motivation of Korean drama were entertainment/relaxation(Vietnam) and longing for actor(actress)(Philippines), respectively. In addition, two path analyses showed that viewing motivations had a significant influence on general attitude toward Korean drama. Longing for actor(actress) and entertainment/relaxation motivations were critical factors in both countries' paths, but habit motivation was negatively related to general attitude toward Korean drama. In case of Korea's national image, the results showed that the more positive general attitude toward Korean drama, the more positive images of national image. Conclusions, implications, and limitations were also discussed.

• Journal of the Korea Society for Simulation
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• v.17 no.4
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• pp.133-142
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• 2008

AGV systems are widely used to increase the flexibility and the efficiency of the material handling systems. AGV systems are one of critical factors which determine the overall performance of the manufacturing systems. To this end, the optimal design for AGV systems is essential. Commercial simulation software is often used as an analysis tool during the design of AGV systems, however a series of procedures are desirable to simplify the analysis processes. In this paper, we present and develop the architecture for unidirectional AGV systems simulator which is able to consider approximate optimal unidirectional flow path and various operational parameters. The designed AGV systems simulator is based on JAVA, and it is developed to support designing approximate optimal unidirectional network by using Tabu search method. In addition, it enables users to design and evaluate AGV systems and to analyze alternative solutions easily. Simulation engine is consists of layout designer, AGV operation plan designer, and integrated AGVS layout designer. Users enter their system design/operation information into input window, then the entered information is automatically utilized for modeling and simulating AGV systems in simulation engine. By this series of procedures, users can get the feed back quickly.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• 2008.11a
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• pp.85-92
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• 2008

Demolition work is a precedence activity that is performed earlier than other remodeling activities. And demolition work is one of the critical path activities. So, demolition work is needed for systematic plan and management. However, contractors of the remodeling project established a rough plan and did not consider recycling wastes, safety of workers and structural stable of building. To improve this problem, a eco-friend process model of remodeling project is needed to be established. The process model is composed of five phases; 1) survey and analysis of general condition of demolition work, 2) prepare documents of demolition work 3) establishing demolition work plan, 4) demolition and inspection, 5) post-demolition management. Especially, demolition documents are based on establishing WBS, selecting the equipment and method, waste management and structure reinforcement. A process model of eco-friend demolition work is developed by using IDEF0 method.