• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.53-61
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• 2004

In this paper, we proposed a new architecture of MAC(Multiplier-Accumulator) to operate high-speed multiplication-accumulation. We used the MBA(Modified radix-4 Booth Algorithm) which is based on the 1's complement number system, and CSA(Carry Save Adder) for addition of the partial products. During the addition of the partial product, the signed numbers with the 1's complement type after Booth encoding are converted in the 2's complement signed number in the CSA tree. Since 2-bit CLA(Carry Look-ahead Adder) was used in adding the lower bits of the partial product, the input bit width of the final adder and whole delay of the critical path were reduced. The proposed MAC was applied into the DWT(Discrete Wavelet Transform) filtering operation for JPEG2000, and it showed the possibility for the practical application. Finally we identified the improved performance according to the comparison with the previous architecture in the aspect of hardware resource and delay.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2006.05a
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• pp.373-378
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• 2006

Recently the technical advances and complexities have generated much of the difficulties in managing the project resources, for both scheduling and costing to accomplish the project in the most efficient manner. The project manager is frequently required to render judgments concerning the schedule and resource adjustments. This research develops an analytical model for a schedule-cost and risk analysis based on visual PERT/CPM. We used a three-step approach: 1) in the first step, a deterministic PERT/CPM model for the critical path and estimating the project time schedule and related resource planning and we developed a heuristic model for crash and stretch out analysis based upon a time-cost trade-off associated with the crash and stretch out of the project. 2) In second step, we developed web-based risk evaluation model for project analysis. Major technologies used for this step are AHP (analytic hierarchy process, fuzzy-AHP, multi-attribute analysis, stochastic network simulation, and web based decision support system. Also we have developed computer programs and have shown the results of sample runs for an R&D project risk analysis. 3) We developed an optimization model for project resource allocation. We used AHP weighted values and optimization methods. Computer implementation for this model is provided based on GUI-Type objective-oriented programming for the users and provided displays of all the inputs and outputs in the form of GUI-Type. The results of this research will provide the project managers with efficient management tools.

• Journal of IKEEE
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• v.19 no.3
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• pp.342-348
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• 2015

High speed implementation of digital filters is required in high data rate applications such as hard-wired wide band modem and high resolution video codec. Since the critical path of the digital filter is the MAC (multiplication and accumulation) circuit, the filter coefficient with sparse non-zero bits enables high speed implementation with adders of low hardware cost. Compressive sensing has been reported to be very successful in sparse representation and sparse signal recovery. In this paper a filter design method for digital FIR filters with CSD (canonic signed digit) coefficients using compressive sensing technique is proposed. The sparse non-zero signed bits are selected in the greedy fashion while pruning the mistakenly selected digits. A few design examples show that the proposed method can be utilized for designing sparse CSD coefficient digital FIR filters approximating the desired frequency response.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.39-48
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• 2005

This paper proposes a reconfigurable coprocessor for communication systems, which can perform high speed computations and various functions. The proposed reconfigurable coprocessor can easily implement communication operations, such as scrambling, interleaving, convolutional encoding, Viterbi decoding, FFT, etc. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18$\mu$m standard cell library. The gate count is about 35,000 gates and the critical path is 3.84ns. The proposed coprocessor can reduced about $33\%$ for FFT operations and complex MAC, $37\%$ for Viterbi operations, and $48\%\~84\%$ for scrambling and convolutional encoding for the IEEE 802.11a WLAN standard compared with existing DSPs. The proposed coprocessor shows Performance improvements compared with existing DSP chips for communication algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.50-57
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• 2000

We propose a logic synthesis algorithm for the design of FPGAs operating at high speed. FPGA is a novel technology that provides programmability in the field. Because of short turnaround time and low manufacturing cost, FPGA has been noticed as an ideal device for system prototyping. Despite these merits, FPGA has drawbacks, namely low integration and long delay time comparing to ASIC. The proposed algorithm partitions a given circuit into subcircuits utilizing a kernel divisor such that the subcircuits can be performed at the same time, hence reducing the delay of the circuit. Experimental results on the MCNC benchmark show that the proposed algorithm is effective by generating circuits having 19.1% les delay on average, when compared to the FlowMap algorithm.

• The Journal of Information Technology
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• v.6 no.4
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• pp.11-23
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• 2003

We proposes that Design of the Digital Neuron Processor and Development of the Algorithm for the real time object recognition in the making Automatic system which uses the residue number system making the high speed operation possible without carry propagation, in this paper. Consisting of MAC(Multiplication and Accumulation) operator unit using Residue number system and sigmoid function operator unit using Mixed Residue Conversion is designed. The Designed circuits are descripted by C language and VHDL and synthesized by Compass tools. Finally, the designed processor is fabricated in 0.8${\mu}m$ CMOS process. Result of simulations shows that critical path delay time is about 19nsec and operation speed is 0.6nsec and the size can be reduced to 1/2 times co pared to the neural networks implemented by the real number operation unit. The proposed design the digital neuron processor can be implemented of the object recognition in the making Automatic system with desired real time processing.

• The Research Journal of the Costume Culture
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• v.25 no.5
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• pp.682-693
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• 2017

The purpose of the study was to compare two different MBTI personality types by evaluating the influence of perceived risk on brand and store loyalty and purchase intention. 340 questionnaires were used for the analysis. For statistical analysis, SPSS 20.0 and AMOS 20.0 were performed, and frequency tests, reliability analyses and Structural Equation Modeling were used. The results of SEM analysis, confirmed that one question of brand loyalty and one question of store loyalty were inappropriate for this study. Thus, these two questions were removed and the research model was modified. To determine the goodness of fit of the research model, convergent validity was tested. Most items fell into the goodness of fit, and the average coefficient was fulfilled. According to the results of a path coefficient analysis for the Judging type, perceived risk has a significant influence on brand loyalty and brand loyalty also affected store loyalty. Furthermore, brand loyalty and store loyalty have a significant effect on purchase intentions, but perceived risk did not affect brand loyalty for the Perceiving type. Brand loyalty influences store loyalty and purchase intentions, but store loyalty did not influence purchase intentions. As a result of this study, it is concluded that considering consumers' personality types is critical to developing strategies that enhance brand loyalty.

• Journal of Advanced Navigation Technology
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• v.22 no.5
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• pp.415-419
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• 2018

This paper predicts and measures the C/N ratio of a beacon signal transmitted from geostationary orbit satellite KorSat 5A ($113^{\circ}E$) at a ground station located in Kimpo. Based on the ground stations, we compared the rain attenuation of the zone K of ITU-R and the rain attenuation which analyzed the domestic weather information. In ITU-R, the Korean rainfall characteristics are classified into zone K, but forecasting the rainfall intensity and attenuation of three adjacent cities based on the cumulative rainfall data per minute from 2013 to 2017. The calculation of rainfall path and attenuation is based on ITU-R recommendations. The change of the C/N according to the rainfall amount was confirmed through the 2 week satellite beacon signal C/N measurement. The predicted critical C/N was decreased to 12 dB at $A_{0.3}$. During the experiment, it was confirmed that it decreased up to 8 dB according to the concentrated rainfall.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2367-2372
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• 2015

One of various low-density parity-check(LDPC) codes that has been adopted in many communication standards due to its error correction ability is a quasi-cyclic LDPC(QC-LDPC) code, which leads to comparable decoder complexity. One of the main blocks in the QC-LCDC code decoder is a multi-size circular shifter(MSCS) that can perform various size rotation. The MSCS can be implemented with many structures, one of which is based on Banes network. The Benes network structure can perform the normal MSCS operation efficiently, but it cannot use the properties coming from specifications like rotation sizes. This paper proposesd a scheme where the Benes network structure can use the rotation size property with the modification of the control signal generation. The proposed scheme is applied to the MSCS of IEEE 802.16e WiMAX QC-LDPC decoder to reduce the number of MUXes and the critical path delay.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.112-121
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• 2002

In this paper, we present a design of a hash processor for data security systems. Two standard hash algorithms, Sha-1(American) and HAS-1600(Korean), are implemented on a single hash engine to support real time processing of the algorithms. The hash processor can also be used as a PRNG(Pseudo-random number generator) by utilizing SHA-1 hash iterations, which is being used in the Intel software library. Because both SHA-1 and HAS-160 have the same step operation, we could reduce hardware complexity by sharing the computation unit. Due to precomputation of message variables and two-stage pipelined structure, the critical path of the processor was shortened and overall performance was increased. We estimate performance of the hash processor about 624 Mbps for SHA-1 and HAS-160, and 195 Mbps for pseudo-random number generation, both at 100 MHz clock, based on Samsung 0.5um CMOS standard cell library. To our knowledge, this gives the best performance for processing the hash algorithms.