• Title/Summary/Keyword: Counter Mode

Search Result 125, Processing Time 0.028 seconds

All-optical Internodal Switching in Two-mode Waveguide (이중모드 광섬유내에서의 전 광(All-optical) 모드 변환 스위칭)

  • 박희갑
    • Proceedings of the Optical Society of Korea Conference
    • /
    • 1989.02a
    • /
    • pp.119-122
    • /
    • 1989
  • An intermodal switch based on optically-induced (through optical Kerr effect) periodic coupling in a two-mode waveguide is described and demonstrated. A high power pump beam injected into the two modes of the waveguide produced a periodic modulation of the refractive index profile with a period of modal beat length. this causes an intermodal coupling of the prove beam. The operating principle was successfully demonstrated in an elliptical core two-mode fiber with a counter-propagating pump-probe scheme.

  • PDF

On the Conceptual Design of the SIMD Vector Machine Attachable to SISD Machine (SISD 머신에 부착 가능한 SIMD 벡터 머신의 개념적 설계)

  • Cho Young-Il;Ko Young-Woong
    • The KIPS Transactions:PartA
    • /
    • v.12A no.3 s.93
    • /
    • pp.263-272
    • /
    • 2005
  • The addressing mode for data is performed by the software in yon Neumann-concept(SISD) computer a priori without hardware design of an address counter for operands. Therefore, in the addressing mode for the vector the corresponding variables as much as the number of the elements should be specified and used also in the software method. This is because not for operand but only for an instructions, quasi PC(program counter) is designed in hardware physically. A vector has a characteristic of a structural dimension. In this paper we propose to design a hardware unit physically external to the CPU for addressing only the elements of a vector unit with the structure and dimension. Because of the high speed performance for a vector processing it should be designed in the SIMD pipeline mechanics. The proposed mechanics is evaluated through a simulation. Our result shows $12\%$ to $30\%$ performance enhancement over CRAY architecture under the same hardware consideration(processing unit).

Efficiency Counter Electrode Discharge Cells of PDP - a macro-cell experiment

  • Kim, Young-Jin;Choi, Won-Youl;Kim, Jin-Seok;Kim, Yong-seog;Choi, Byung-Do
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 2005.07a
    • /
    • pp.255-258
    • /
    • 2005
  • In this study, new types of counter electrode discharge cells for PDP were designed. The counter electrode discharge cells were designed to realize long-gap discharge mode, low firing voltage and moderate conductance for evacuation and sealing process of the panel. In order to test the concept of the design, macro discharge cells were prepared and the discharge characteristics were evaluated. The results indicate that discharge behavior may be modified significantly by changing the morphology of discharge cells.

  • PDF

A Study on the Formal Characteristics of Theo van Doesburg's Counter-construction - Focus on the House Projects in 1923 De Stijl Exhibition - (테오 판 두스부르흐의 반-구축적 조형특성에 관한 연구 - 1923년 데 스틸 전시회의 주택설계작품을 중심으로 -)

  • Suh, Jeong-Yeon
    • Korean Institute of Interior Design Journal
    • /
    • v.19 no.3
    • /
    • pp.30-37
    • /
    • 2010
  • Dutch artist, Theo van Doesburg had shown short but strong experimental aesthetics in his works through De Stijl movement. He played a leading role for editing De Stijl magazine and performed various formative works such as painting, sculpture, and architecture. In 1923 he opened the first De Stijl exhibition cooperated with Cornelis van Eesteren. In this architecture exhibition he showed rich formal spirits of counter-construction in his major design works, that is Maison Particuliere and Maison D'artiste among three houses projects. Formal characteristics of counter-construction can be summed up under two categories, time and space. Analytical results are as follows; First, the characteristics of counter-construction related to time category include two types of two mode. One is linear aspect of time based on the viewer's movement. The other aspect is simultaneity caused by synoptical effect. These could be proved by the analysis of arrangement of color planes. Secondly, the spatial aspects of counter-construction are produced through two different ways of formal strategies. Van Doesburg arranged cubes in very irregular pattern. This treatment induces ambiguous void and creates feeling of subject's space. And, through deleting, shifting, and extending he could make dynamic spatial effect by interpenetration between in and out. This fluid space thus introduces movements of one's gaze and circulation. He denied traditional classical values which had ruled the western aesthetical discipline for centuries and believed that mankind can reach the realm of universal equilibrium by contrast and tension created by counter-construction. In this vein Theo van Doesburg was an avant-garde artist of Hegelian thoughts who adopted the dialectical method without following the formal characteristics from ancestors.

Monitoring of Airborne Fine Particle using SMPS in Ansan Area (SMPS(Scanning Mobility Particle Sizer)를 이용한 안산지역 대기중 초미세입자(30\~500nm) 분포연구)

  • Kim Yong-min;Ahn Kang-Ho
    • Journal of Korean Society for Atmospheric Environment
    • /
    • v.21 no.3
    • /
    • pp.295-301
    • /
    • 2005
  • The fine particles in the range of $30\~500nm$ are monitored at Hanyang University campus in Ansan using house made DMA (differential mobility analyzer) and commercial CPC (condensation particle counter, TSI inc.) in SMPS mode. The monitoring period is March 16th 2004 through May 7th, 2004. During the monitoring period, Aitken nuclei mode $(30\~100nm)$ particle concentration has a tendency of increase in the morning and evening hours. However, the accumulation mode $(100\~500nm)$ particle concentration stays rather stable than that of Aitken mode.

A Cryptographic Processor Supporting ARIA/AES-based GCM Authenticated Encryption (ARIA/AES 기반 GCM 인증암호를 지원하는 암호 프로세서)

  • Sung, Byung-Yoon;Kim, Ki-Bbeum;Shin, Kyung-Wook
    • Journal of IKEEE
    • /
    • v.22 no.2
    • /
    • pp.233-241
    • /
    • 2018
  • This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.

A Novel Fast-Switching LCD with Dual-Domain Bend Mode

  • Satake, Tetsuya;Kurata, Tetsuyuki
    • Journal of Information Display
    • /
    • v.5 no.2
    • /
    • pp.39-42
    • /
    • 2004
  • A novel fast-switching LCD with dual-domain bend (DDB) mode is described. DDB alignment is achieved using antiparallel-rubbed cell filled with chiral-doped LC. Initial alignment is mono-domain 180-degree twist. Tilt direction is controlled by oblique electric field to be counter direction in each domain. Twist-to-DDB deformation occurs continuously so that DDB mode does not require high-voltage initialization which is inevitable in Optically Compen sated Bend (OCB) mode. DDB gives wide and symmetric viewing angle in contrast to mono-domain bend formed from 180-degree twist showing strong asymmetry.

Wide-Input Range Dual Mode PWM / Linear Buck Converter with High robustness ESD Protection Circuit

  • Song, Bo-Bae;Koo, Yong-Seo
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.15 no.2
    • /
    • pp.292-300
    • /
    • 2015
  • This paper proposes a high-efficiency, dual-mode PWM / linear buck converter with a wide-input range. The proposed converter was designed with a mode selector that can change the operation between PWM / linear mode by sensing a load current. The proposed converter operates in a linear mode during a light load and in PWM mode during a heavy load condition in order to ensure high efficiency. In addition, the mode selector uses a bit counter and a transmission gate designed to protect from a malfunction due to noise or a time-delay. Also, in conditions between $-40^{\circ}C$ and $140^{\circ}C$, the converter has variations in temperature of $0.5mV/^{\circ}C$ in the PWM mode and of $0.24mV/^{\circ}C$ in the linear mode. Also, to prevent malfunction and breakdown of the IC due to static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class(Chip level) ESD protection circuit of a P-substrate Triggered SCR type with high robustness characteristics.

A Design of Authentication/Security Processor IP for Wireless USB (무선 USB 인증/보안용 프로세서 IP 설계)

  • Yang, Hyun-Chang;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.12 no.11
    • /
    • pp.2031-2038
    • /
    • 2008
  • A small-area and high-speed authentication/security processor (WUSB_Sec) IP is designed, which performs the 4-way handshake protocol for authentication between host and device, and data encryption/decryption of wireless USB system. The PRF-256 and PRF-64 are implemented by CCM (Counter mode with CBC-MAC) operation, and the CCM is designed with two AES (Advanced Encryption Standard) encryption coles working concurrently for parallel processing of CBC mode and CTR mode operations. The AES core that is an essential block of the WUSB_Sec processor is designed by applying composite field arithmetic on AF$(((2^2)^2)^2)$. Also, S-Box sharing between SubByte block and key scheduler block reduces the gate count by 10%. The designed WUSB_Sec processor has 25,000 gates and the estimated throughput rate is about 480Mbps at 120MHz clock frequency.

Output Voltage Regulation for Harmonic Compensation under Islanded Mode of Microgrid

  • Lim, Kyungbae;Choi, Jaeho
    • Journal of Power Electronics
    • /
    • v.17 no.2
    • /
    • pp.464-475
    • /
    • 2017
  • This study examines a P+multi resonant-based voltage control for voltage harmonics compensation under the islanded mode of a microgrid. In islanded mode, the inverter is defined as a voltage source to supply the full local load demand without the connection to the grid. On the other hand, the output voltage waveform is distorted by the negative and zero sequence components and current harmonics due to the unbalanced and nonlinear loads. In this paper, the P+multi resonant controller is used to compensate for the voltage harmonics. The gain tuning method is assessed by the tendency analysis of the controller as the variation of gain. In addition, this study analyzes the slight voltage magnitude drop due to the practical form of the P+multi resonant and proposes a counter method to solve this problem by adding the PI-based voltage restoration method. The proposed P+multi resonant controller to compensate for the voltage harmonics is verified through the PSIM simulation and experimental results.