• Journal of the Microelectronics and Packaging Society
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• v.20 no.1
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• pp.1-5
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• 2013

Wafer-to-Wafer (W2W) integration technology is an emerging technology promising many benefits, such as reduced size, improved performance, reduced power, lower cost, and divergent integration. As the maturity of W2W technology progresses, new applications will become more viable. However, at present the cost for W2W integration is still very high and both manufacturing yield and reliability issues have not been resolved yet for high volume manufacturing (HVM). Especially for WTW integration resolving compound yield issue can be a key factor for HVM. To have the full benefits of WTW integration technology more than simple wafer stacking technologies are necessary. In this paper, the manufacturing yield for W2W integration is described and the challenges of WTW integration will be discussed.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.5_6
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• pp.299-306
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• 2003

This paper formulates a problem of embedded real-time system re-engineering, and presents its solution approach. Embedded system re-engineering is defined as a development task of meeting performance requirements newly imposed on a system after its hardware and software have been fully implemented. The performance requirements nay include a real-time throughput and an input-to-output latency. The proposed solution approach is based on a bottleneck analysis and nonlinear optimization. The inputs to the approach include a system design specified with a process network and a set of task graphs, task allocation and scheduling, and a new real-time throughput requirement specified as a system's period constraint. The solution approach works in two steps. In the first step, it determines bottleneck precesses in the process network via estimation of process latencies. In the second step, it derives a system of constraints with performance scaling factors of processing elements being variables. It then solves the constraints for the performance staling factors with an objective of minimizing the total hardware cost of the resultant system. These scaling factors suggest the minimal cost hardware upgrade to meet the new performance requirement. Since this approach does not modify carefully designed software structures, it helps reduce the re-engineering cycle.

• Structural Engineering and Mechanics
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• v.80 no.5
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• pp.503-522
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• 2021

This paper investigates experimentally and numerically the influence of drilling process on the mechanical and thermomechanical behaviors of woven glass fiber reinforced polymer (GFRP) composite plate. Through the experimental analysis, a CNC machine with cemented carbide drill (point angles 𝜙=118° and 6 mm diameter) was used to drill a woven GFRP laminated squared plate with a length of 36.6 mm and different thicknesses. A produced temperature during drilling "heat affected zone (HAZ)" was measured by two different procedures using thermal IR camera and thermocouples. A thrust force and cutting torque were measured by a Kistler 9272 dynamometer. The delamination factors were evaluated by the image processing technique. Finite element model (FEM) has been developed by using LS-Dyna to simulate the drilling processing and validate the thrust force and torque with those obtained by experimental technique. It is found that, the present finite element model has the capability to predict the force and torque efficiently at various drilling conditions. Numerical parametric analysis is presented to illustrate the influences of the speeding up, coefficient of friction, element type, and mass scaling effects on the calculated thrust force, torque and calculation's cost. It is found that, the cutting time can be adjusted by drilling parameters (feed, speed, and specimen thickness) to control the induced temperature and thus, the force, torque and delamination factor in drilling GFRP composites. The delamination of woven GFRP is accompanied with edge chipping, spalling, and uncut fibers.

• Journal of Korea Society of Industrial Information Systems
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• v.25 no.2
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• pp.39-47
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• 2020

This paper introduces a novel system-level framework that derives energy efficient electric vehicle (EV) driving speed profile to extend EV driving range without additional cost. This paper first implements an EV power train model considering forces acting on a driving vehicle and motor efficiency. Then, it derivate the minimum-energy driving speed profile for a given driving mission defined by the route. This framework first formulates an optimization problem and uses the dynamic programming algorithm with a weighting factor to derive a speed profile minimizing both of energy consumption and driving time. This paper introduces various weighting factor tracking methods to satisfy the driving time constraint. Simulation results show that runtime of the proposed scaling algorithm is 34% and 50% smaller than those of the binary search algorithm and greedy algorithm, respectively.

• Composites Research
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• v.36 no.1
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• pp.42-47
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• 2023

In this paper, we present a fatigue life prediction methodology using multiple S-N curves according to the different stress states of laminated composites. The stress states of the plies of the laminated composites are classified into five modes: longitudinal tension or compression and transverse tension or compression, and shear according to the maximum stress criterion and Puck's criterion with a scaling factor K. This methodology has advantages in computational cost, and it can also consider microstructural characteristics of the composites by applying different S-N curves. The S-N curves for the fatigue analysis are obtained by experimental fatigue test. The proposed methodol is implemented into commercial software, ABAQUS user material subroutine and therefore, the fatigue analysis is conducted using the structural analysis results. The finite element (FE) simulation results are presented for unidirectional composites with and without open-hole. The FE simulation results show that the stress condition is different depending on the fiber orientation of the unidirectional composite, so the fatigue life is calculated with different S-N curves.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.1-9
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• 2010

Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.11-19
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• 2015

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.