• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.2074-2079
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• 2018

Global state space's optimal policy is used for offline controller in the form of table by using Dynamic Programming. If an optimal policy table has a large amount of control data, it is difficult to use the system in a low capacity system. To resolve these problem, controller using the compressed optimal policy table is proposed in this paper. A DCT is used for compression method and the cosine function is used as a basis. The size of cosine function decreased as the frequency increased. In other words, an essential information which is used for restoration is concentrated in the low frequency band and a value of small size that belong to a high frequency band could be discarded by quantization because high frequency's information doesn't have a big effect on restoration. Therefore, memory could be largely reduced by removing the information. The compressed output is stored in memory of embedded system in offline and optimal control input which correspond to state of plant is computed by interpolation with Inverse DCT in online. To verify the performance of the proposed controller, computer simulation was accomplished with a one link inverted pendulum.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.465-468
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• 2001

MPEG-4 Parametric Coding 중 저 비트율로 음성신호를 부호화하는 HVXC(Harmonic Vector excitation Ending)의 복호화 모듈인 LSP 합성필터와 무성음 합성부, 유성음 합성부를 VHDL을 이용하여 구현하였다. MPEG-4 HVXC의 복호화 과정은 코드북을 이용하여 LSP 계수, VXC signal, 그리고 Spectral Envelop이 복호화 되어 각각 LSP 역필터, 무성음과 유성음 합성단을 통과하여 LPC계수와 유,무성음 여기신호로 변환된 후 LPC 합성필터링 과정을 거쳐 최종적으로 음성신호를 출력시킨다. LSP inverse filter에서 사용되는 cosine함수값을 위하여 Table based Approximation을 이용하여 적은 양의 Table 값을 사용하여 정확하고 고속의 cosine 연산을 수행하였다. VXC 복호화 과정에서는 신호의 중복성을 제거하는 Hidden Address in LSH 방법을 사용하여 코드북의 크기를 줄였다. 유성음 합성단에서는 IFFT 모듈을 이용하여 연산속도를 증가 시켰다. 최종적으로 위와 같이 구현된 시스템을 Simulation을 통해 Software 검증을 하였다.

• Journal of Biomedical Engineering Research
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• v.13 no.4
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• pp.323-330
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• 1992

A Study of Image Compression Algorithm using DCT This paper describes the system that implement a JPEG(Joint Photographic Experts Group) algorithm based on DCT(Discrete Cosine Transform) uslng CCD kameva, Image Grabber, and IBM PC. After cosine transforms the acquisited image, this algorithm quantize and entropy encode the coefficients by JPEG code table. The coefficients are reconstructed by the Huffman decoding, dequantized procedure, and Inverse cosine transform. The results obtained from the impleulented system are as follows. (1) For effcient storage and easy implementation, this system save Image as a PCX formal (2) Thls system get 7:1 compression ratio(3.8 RMSE value) without large distortion. (3) With a low pass filtering, thls system eliminate high frequency components and get 20% enhanced compression ratio. (4) Thls system enhance the reconstructed Image using histogram modeling.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.907-910
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• 2000

QPSK 복조기는 위상 오차에 따른 문제점을 극복하기 위해 수신단에서는 반송파의 주파수와 위상을 tracking 하는 Carrier recovery loop부분이 필요하다〔1〕. Carrier recovery loop는 multiplier, arm filter, matched filter, decimator, loop filter, NCO로 구성이 된다〔2〕.기존 Carrier recovery loop의 NCO는 sine과 cosine의 lookup table을 갖는 구조로 되어있어, 전력소모가 크다는 문제점을 가지고 있다. 따라서 본 논문에서는 lookup table을 사용하지 않는 저 전력 구조의 QPSK복조기의 Carrier recovery loop의 NCO를 설계했다.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.13 no.6
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• pp.41-47
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• 2004

This study is aimed to measure the deflection of loaded table on machine tool. The deflection rate is measured then the table is in a stationary state and is moved. In conclusion we have found that the more load increases, the more the table deflections. Also, we have found that the deflection rate increases in accordance with the speed of movement. Therefore, we have concluded that inspection of machine tool should be done considering the weight of load and the speed of movement. However, since the condition of accuracy test for domestic brand of machine tool is defined as unloaded case, measures should be explored only for loaded case.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.411-414
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• 2008

The study is about simulation of optical circuit for oneself performance evaluation of Fiber Optic Gyro(FOG) closed-loop controller board. The Fiber Optic Interferometer Simulator is used a digital signal processing for cosine response specificity output of fiber optic coil about input rate. Response specificity of the fiber optic coil is $Vo(t)=K3[1+\cos\{K1(Vm(t)-Vm(t-{\tau}))+K2\}]$. Also the Fiber Optic Interferometer Simulator is able to confirm a output value with K1, K2 and K3 input. The fiber Optic Interferometer Simulator is able to oneself performance evaluation without fiber optical circuit. Because, it is the very same cosine response specificity of real fiber optic coil about input rate.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.360-363
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• 1999

Video data compression is a major key technology in the field of multimedia applications. Variable-length coding is the most popular data compression technique which has been used in many data compression standards, such as JPEG, MPEG and image data compression standards, etc. In this paper, we present memory efficient VLC decoder architecture for MPEG-2 application which can achieve small memory space and higher throughput. To reduce the memory size, we propose a new grouping, remainder generation method and merged lookup table (LUT) for variable length decoders (VLD's). In the MPEG-2, the discrete cosine transform (DCT) coefficient table zero and one are mapped onto one memory whose space requirement has been minimized by using efficient memory mapping strategy The proposed memory size is only 256 words in spite of mapping two DCT coefficient tables.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.2
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• pp.37-43
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• 2009

In this study, multi-channel digital hearing aid algorithm for low power system is proposed. First, MDCT(Modified Discrete Cosine Transform) method converts time domain of input speech signal into frequency domain of it. Output signal from MDCT makes a group about each channel, and then each channel signal adjusts a gain using LCF(Loudness Compensation Function) table depending on hearing loss of an auditory person. Finally, compensation signal is composed by TDAC and IMDCT. Its all of process make progress 16-bit fixed-point operation. We use fast-MDCT instead of MDCT for reducing system complexity and previously computed tables instead of log computation for estimating a gain. This algorithm evaluate through computer simulation.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.1
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• pp.35-41
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• 2000

This paper considers the consturction of 24/25 I-NRZI (Interleaved - Non Return to Zero Inverse) modulator designs for DVCR (Digital Video Cassette Recorder), and size of validity bit in order to store the amplitude value of square-wave and the standard data ( sine and cosine coefficients) at ROM Table that to acceptable the spectrum standard. The validity bit size of the standard data and the amplitude value of square-wave that to store at ROM Table are affected the size of pilot signal on the output spectrum, and the hardware size of modulator. At the designable 24/25 I-NRZI modulator, we simulated using random pattern (F0,F1,F2) that to verification the output data of the spectrum. Moreover, the resultant of the spectrum analysis, at the optimizing value, is 0.065 on the amplitude value of square-wave, and 3bit on the size of bit in order to store the standared data at ROM Table. In order to verify the hardware of designable 24/25 I-NRZI modulator, we perform to modeling of C-language firstly, and coding to Verilog HDL (Cadence Verilog XL) and synthesized using Synopsys (Library "Samsung KG75") tool as a base of spectrum results. In a foundation of this result, we are considered the size of hardware. In this paper, a considerable 24/25 I-NRZI modulator designable less than 10,000 gates as that is improved consturction as regards the path method of pre-coder etc, and able to application digital camcorders as now practical use.