• Title/Summary/Keyword: Core simulation

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Core-loss reduction on PM for IPMSM with concentrated winding (집중권을 시행한 영구자석 매입형 동기전동기의 철손 저감)

  • Lee, Hyung-Woo;Park, Chan-Bae;Lee, Byung-Song;Kim, Nam-Po
    • Proceedings of the KSR Conference
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    • 2011.10a
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    • pp.1832-1837
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    • 2011
  • This paper presents the optimal permanent magnet shape on the rotor of an interior permanent magnet motor to reduce the core losses and improve the performance. As permanent magnet has conductivity inherently, it causes huge amount of eddy current losses by the slot harmonics with concentrated winding. This loss is roughly 100 times larger than that of distributed winding in high speed operation and it cannot be ignored, especially on traction motors. Each eddy current loss on permanent magnet has been investigated in detail by using FEM(Finite Element Method) instead of EMCNM(Equivalent Magnetic Circuit Network Method) in order to consider saturation and non-linear magnetic property. Simulation-based DOE(Design Of Experiment) is also applied to avoid large number of analyses according to each design parameter and consider expected interactions among parameters. Consequently, the optimal design to reduce the core loss on the permanent magnet while maintaining or improving motor performance is proposed by an optimization algorithm using regression equation derived and lastly, the core loss reduction on the proposed shape of the permanent magnet is verified by FEM.

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A Performance Study of Embedded Multicore Processor Architectures (임베디드 멀티코어 프로세서의 성능 연구)

  • Lee, Jongbok
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.13 no.1
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    • pp.163-169
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    • 2013
  • Recently, the importance of embedded system is growing rapidly. In-order to satisfy the real-time constraints of the system, high performance embedded processor is required. Therefore, as in general purpose computer systems, embedded processor should be designed as multicore architecture as well. Using MiBench benchmarks as input, the trace-driven simulation has been performed and analyzed for the 2-core to 16-core embedded processor architectures with different types of cores from simple RISC to in-order and out-of-order superscalar processors, extensively. As a result, the achievable performance is as high as 23 times over the single core embedded RISC processor.

Laboratory investigation of the effects of translation on the near-ground tornado flow field

  • Razavi, Alireza;Sarkar, Partha P.
    • Wind and Structures
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    • v.26 no.3
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    • pp.179-190
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    • 2018
  • Translation of tornadoes is an important feature in replicating the near-ground tornado flow field which has been simulated in previous studies based on Ward-type tornado simulators using relative motion of the ground plane. In this laboratory investigation, effects of translation on the near-ground tornado flow field were studied using the ISU Tornado Simulator that can physically translate over a ground plane. Two translation speeds, 0.15 m/s and 0.50 m/s, that scale up to those corresponding to slowly-moving tornadoes in the field were selected for this study. Compared with the flow field of a stationary tornado, the simulated tornado with translation had an influence on the spatial distribution and magnitude of the horizontal velocities, early reversal of the radial inflow, and expansion of the core radius. Maximum horizontal velocities were observed to occur behind the center of the translating tornado and on the right side of its mean path. An increase in translation speed, resulted in reduction of maximum horizontal velocities at all heights. Comparison of the results with previous studies that used relative motion of the ground plane for simulating translating tornadoes, showed that translation has similar effects on the flow field at smaller radial distances (~2 core radius), but different effects at larger radial distances (~4 core radius). Further, it showed that the effect of translation on velocity profiles is noticeable at and above an elevation of ~0.6 core radius, unlike those in studies based on the relative motion of the ground plane.

Temperature Properties about SMD Inductor Core of Union Type (일체형 SMD Inductor 코어에 대한 온도 특성)

  • Kim, Ki-Joon
    • 전자공학회논문지 IE
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    • v.47 no.2
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    • pp.32-37
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    • 2010
  • In this study, to develop union type SMD inductor core needs to have the desire of super miniaturization and high reliability, it analyzed temperature properties due to electric power value. As the temperature of electronic parts rise, it bring to technical obstacles that parts can not normal operation, it reduce the span of life to raise the fault ratio. Also, it impact to the parts by heat change power and expansive power, it can not behave exactly, and it have an effect on reliability. It measured the difference value between conditional temperature and parts temperature to union type SMD inductor core. As the results of simulation using D.C. current and resistor($R_dc$), it obtained the excellent regular current values at rising temperature of 40[$^{\circ}C$].

Performance Development of Coolant Core for Range Extender Engine Using CFD Simulation (전산유체해석을 통한 RE엔진 냉각수 코어의 성능 개발)

  • Kim, Chang-Su;Park, Sung-Young
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.14 no.5
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    • pp.2075-2080
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    • 2013
  • A Coolant core for Range Extender engine has been developed using CFD technique. Coolant by-pass has been added to the improved model to reduce temperature near and between exhaust valve. Due to the increased coolant flow-rate both around the second cylinder block and between exhaust valves, improved model shows no significant stagnant flow compared with base model. Finally, the improved model shows improved heat transfer coefficients near exhaust valves, and 5% reduced pressure-drop through the coolant core. Reduced pressure-drop may increase the fuel efficiency by reducing the load of a coolant pump.

Low-latency SAO Architecture and its SIMD Optimization for HEVC Decoder

  • Kim, Yong-Hwan;Kim, Dong-Hyeok;Yi, Joo-Young;Kim, Je-Woo
    • IEIE Transactions on Smart Processing and Computing
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    • v.3 no.1
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    • pp.1-9
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    • 2014
  • This paper proposes a low-latency Sample Adaptive Offset filter (SAO) architecture and its Single Instruction Multiple Data (SIMD) optimization scheme to achieve fast High Efficiency Video Coding (HEVC) decoding in a multi-core environment. According to the HEVC standard and its Test Model (HM), SAO operation is performed only at the picture level. Most realtime decoders, however, execute their sub-modules on a Coding Tree Unit (CTU) basis to reduce the latency and memory bandwidth. The proposed low-latency SAO architecture has the following advantages over picture-based SAO: 1) significantly less memory requirements, and 2) low-latency property enabling efficient pipelined multi-core decoding. In addition, SIMD optimization of SAO filtering can reduce the SAO filtering time significantly. The simulation results showed that the proposed low-latency SAO architecture with significantly less memory usage, produces a similar decoding time as a picture-based SAO in single-core decoding. Furthermore, the SIMD optimization scheme reduces the SAO filtering time by approximately 509% and increases the total decoding speed by approximately 7% compared to the existing look-up table approach of HM.

Research on Using Six Sigma Tool to Reduce the Core Process Time

  • Chung, Yi-Chan;Yen, Tieh-Min;Hsu, Yau-Wen;Tsai, Chih-Hung;Chen, Ching-Piao
    • International Journal of Quality Innovation
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    • v.9 no.1
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    • pp.94-102
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    • 2008
  • When facing the global severe competition, the enterprises all try their best to upgrade the quality, reduce the costs to reach the goal of customer satisfaction. Motorola was the earliest firm creating the term Six Sigma (6 ${\sigma}$); GE was the enterprise successfully fulfilling Six Sigma. The success of these two firms revealed the prominent effects and became the world-class model enterprises. The main purpose of promoting Six Sigma activity was to reduce the possible defects in the business process to the least through designing and monitoring business process in order to reach the goals such as the best quality and efficiency, the lowest costs, the shortest circular process time, maximum profits and customer satisfaction. This research used the Six Sigma technique to improve the business process of ceramics manufacturing plant and find out the major factors of slower core task time by the analytical process of Process Mapping, Pareto Chart, Simu18 simulation software and figures and proposed the improvement measures. Through the confirmation of the case companies, it successfully reduced the core process time and the organizational costs and increased the capacity.

Localized Development of Propellant Mixer (추진제 믹서 국산화 개발)

  • Kim, Kyungmoo;Khil, Taeock;Hong, Myungpyo;Doh, Yeunsung
    • Journal of the Korean Society of Propulsion Engineers
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    • v.20 no.1
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    • pp.58-68
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    • 2016
  • The propellant mixer for charging of solid rocket motors is one of the most important equipments. For the propellant mixer is export control item, it's hard to purchase it directly from abroad. The Mixer was developed locally to overcome export control which precludes us from import. This paper includes the introduction for general mixers and the process of mixer development progressed by LIGNex1. Finally, The mixer is verified the performance using measurements of clearance between blade-blade and blade-bowl and flow simulation with ADINA.

Performance Study of Asymmetric Multicore Processor Architectures (비대칭적 멀티코어 프로세서의 성능 연구)

  • Lee, Jongbok
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.14 no.3
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    • pp.163-169
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    • 2014
  • Recently, the importance of multicore processor system is growing rapidly. Multicore processors are classified either as symmetric or asymmetric. Asymmetric multicore processors consist of a high performance complex core and number of low performance simple cores, and are known to be more efficient than symmetric multicore processors. Therefore, performance impact on various configurations of asymmetric multi-core processor needs to be studied. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for different asymmetric quad-core and octa-core processors and compared to the corresponding symmetric ones.

Design and Simulation Technologies of Flat Transformer with High Power Current (대전류 출력형 Flat Transformer 설계 및 해석 기술)

  • Han, Se-Won;Cho, Han-Goo;Woo, Bung-Chul
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.05c
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    • pp.15-17
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    • 2002
  • Leakage inductance and temperature rise are two of the more impotent problems facing the magnetic core technology of today's high frequency transformers. Excessive leakage inductance increases the stress on the switching transistors and limits the duty-cycle, and excessive temperature rise can lead the design limitation of high frequency transformer with high current. The flat transformer technology provides a very good solution to the problems of leakage inductance and thermal management for high frequency power. The critical magnetic components and windings are optimized and packaged within a completely assembled module. The turns ratio in a flat transformer is determined as the product of the number of elements or modules times the number of primary turns. The leakage inductance increase proportionately to the number of elements, but since it is reduced as the square of the turns, the net reduction can be very significant. The flat transformer modules use cores which have no gap. This eliminates fringing fluxes and stray flux outside of the core. The secondary windings are formed of flat metal and are bonded to the inside surface of the core. The secondary winding thus surrounds the primary winding, so nearly all of the flux is captured.

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