• Korean Journal of Mathematics
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• v.19 no.3
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• pp.243-253
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• 2011

We would like to propose a Cooley-Tukey modied algorithm in fast Fourier transform(FFT). Of course, this is a kind of Cooley-Tukey twiddle factor algorithm and we focused on the choice of integers. The proposed algorithm is better than existing ones in speeding up the calculation of the FFT.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.97-105
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• 2015

This paper discusses the implementation of Bruun's FFT on a SIMD processor. FFT is an algorithm used in digital signal processing area and its effective processing is important in the enhancement of signal processing performance. Bruun's FFT algorithm is one of fast Fourier transform algorithms based on recursive factorization. Compared to popular Cooley-Tukey algorithm, it is advantageous in computations because most of its operations are based on real number multiplications instead of complex ones. However it shows more complicated data alignment patterns and requires a larger memory for storing coefficient data in its implementation on a SIMD processor. According to our experiment result, in the processing of the FFT with 1024 complex input data on a SIMD processor, The Bruun's algorithm shows approximately 1.2 times higher throughput but uses approximately 4 times more memory (20 Kbyte) than the Cooley-Tukey algorithm. Therefore, in the case with loose constraints on silicon area, the Bruun's algorithm is proper for the processing of FFT on a SIMD processor.

• Journal of the Korean Professional Engineers Association
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• v.20 no.1
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• pp.14-20
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• 1987

The development of the FHT (fast Hadamard transform) was presented and based on the derivation by Cooley-Tukey algorithm. Alternately, it can be derived by matrix partitioning or matrix factorization techniques. This paper proposes a simple sparse matrix technique by Kronecker product of successive lower Hadamard matrix. The following shows how the Kronecker product can be mathematically defined and efficiently implemented using a matrix factorization methods.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1617-1623
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• 1989

The introduction of the fast Fourier transform(FFT),an efficient computational algorithm for the discrete Fourier transform(DFT) by Cooley and Tukey(1965), has brought to the limelight various other discrete transforms. Some of the analog functions from which these transforms have been derived date back to the early 1920's, for example, Walsh functions (Walsh, 1923) and Hadamard Transform(Enomoto et al, 1965). Fast algorithms developed for the forward transform are equally applicable, exept for minor changes, to the inverse transform. In this paper, we present a simple pipelined Hadamard matrix(HM) which is used to develop a fast algorithm for the Hadamard Processor (HP). The Fast Hadamard Transform(FHT) can be derived using matrix partitioning techniques. The HP system is incorporated through a modular design which permits tailoring to meet a wide range of video data link applications. Emphasis has been placed on a low cost, a low power design suitable for airbone system and video codec.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8B
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• pp.787-795
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• 2002

This paper presents the architecture and the implementation of a 2K/4K/8K-point complex Fast Fourier Transform(FFT) processor for Orthogonal Frequency-Division Multiplexing (OFDM) system. The architecture is based on the Cooley-Tukey algorithm for decomposing the long DFT into short length multi-dimensional DFTs. The transposition memory, shuffle memory, and memory mergence method are used for the efficient manipulation of data for multi-dimensional transforms. Booth algorithm and the COordinate Rotation DIgital Computer(CORDIC) processor are employed for the twiddle factor multiplications in each dimension. Also, for the CORDIC processor, a new twiddle factor generation method is proposed to obviate the ROM required for storing the twiddle factors. The overall 2K/4K/8K-FFT processor requires 600,000 gates, and it is implemented in 1.8 V, 0.18 ${\mu}m$ CMOS. The processor can perform 8K-point FFT in every 273 ${\mu}s$, 2K-point every 68.26 ${\mu}s$ at 30MHz, and the SNR is over 48dB, which are enough performances for the OFDM in DVB-T.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.2
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• pp.106-112
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• 2007

This paper proposes a hybrid architecture algorithm for fast computation of DCT and DFT via recursive factorization. Recursive factorization of DCT-II and DFT transform matrix leads to a similar architectural structure so that common architectural base may be used by simply adding a switching device. Linking between two transforms was derived based on matrix recursion formula. Hybrid acrchitectural design for DCT and DFT matrix decomposition were derived using the generation matrix and the trigonometric identities and relations. Data flow diagram for high-speed architecture of Cooley-Tukey type was drawn to accommodate DCT/DFT hybrid architecture. From this data flow diagram computational complexity is comparable to that of the fast DCT algorithms for moderate size of N. Further investigation is needed for multi-mode operation use of FFT architecture in other orthogonal transform computation.