• KIPS Transactions on Software and Data Engineering
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• v.11 no.7
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• pp.299-306
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• 2022

In recent, sensors embedded in robots, equipment, and circuits have become common, and research for diagnosing device failures by learning measured sensor data is being actively conducted. This failure diagnosis study is divided into a classification model for predicting failure situations or types and a regression model for numerically predicting failure conditions. In the case of a classification model, it simply checks the presence or absence of a failure or defect (Class), whereas a regression model has a higher learning difficulty because it has to predict one value among countless numbers. So, the reason that regression modeling is more difficult is that there are many irregular situations in which it is difficult to determine one output from a similar input when predicting by matching input and output. Therefore, in this paper, we focus on input and output data with periodicity, analyze the input/output relationship, and secure regularity between input and output data by performing sliding window-based input data patterning. In order to apply the proposed method, in this study, current and temperature data with periodicity were collected from MMC(Modular Multilevel Converter) circuit system and learning was carried out using ANN. As a result of the experiment, it was confirmed that when a window of 2% or more of one cycle was applied, performance of 97% or more of fit could be secured.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.658-665
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• 2014

The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for higher resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog converter (DAC) sharing scheme for artificial retinal prostheses. The individual pixel circuits in the stimulator IC share a single 6 bit DAC using the sample-and-hold scheme. The DAC sharing scheme enables the simultaneous stimulation on multiple active pixels with a single DAC while maintaining small size and low power. The layout size of the stimulator circuit with the DAC sharing scheme is reduced to be 51.98 %, compared to the conventional scheme. The stimulator IC is designed using standard $0.18{\mu}m$ 1P6M process. The chip size except the I/O cells is $437{\mu}m{\times}501{\mu}m$.

• Proceedings of the Korean Society of Near Infrared Spectroscopy Conference
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• 2001.06a
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• pp.2101-2101
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• 2001

Near-infrared spectroscopy is now being used in clinical diagnosis as a non-invasive monitor of tissue oxygenation state. However, due to lack of the optical pathlength information within tissues, it is still difficult to quantitate the hemoglobin concentration with present CW techniques. Time-resolved spectroscopy (TRS), which measures temporal profiles of emerging light from tissues, enables to estimate the pathlength distribution within tissues by converting time to distance. Consequently, quantitative measurement of tissue oxygenation is possible by analyzing the data with optical diffusion equation 1) or our Microscopic Beer-Lambert law2). Time-Resolved Spectroscopy System : TRS-1O3) Our TRS-10 system consists of a three-wavelength (759, 797, 833 nm) PLP as pulsed light source, a high speed PMT with high sensitivity and three signal-processing circuits for time-resolved measurement (CFD/TAC, A/D converter and histogram memory). Optical pulse train consisting of 759, 797 and 833nm is generated by PLP at 5㎒ repetition rate and irradiated a sample through a single optical fiber. The diffuse-reflected light from the sample is collected by a bundle fiber and then detected by the PMT for single photon measurement. After being amplified by a following fast amplifier, the electrical signals for each wavelength are picked out by CFD/TAC module. Then, a signal processing circuit integrated the TRS data for each wavelength individually. The simultaneous TRS measurement for three wavelengths achieved without any optical or mechanical switch. Experiment and Results Input and detection fibers of TRS-10 were attached at the human forehead with a fiber separation of 3cm. TRS measurements were continuously performed for about 20 minutes including 2 minutes hyper ventilation. It was observed that the total hemoglobin concentration was decreasing during the hyper ventilation and recovered until 2 minutes after hyper ventilation. On the other hand, the deoxy-hemoglobin concentration began to increase after hyper ventilation and had its peak at around 2 minute later, showing 502 drop from 75% to 60% due to inhibition of breathing by performing hyper ventilation. The results showed that this system might be able to quantitate the concentrations of oxy- and deoxy-hemoglobin in the human brain.

• Journal of Electrical Engineering and Technology
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• v.4 no.2
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• pp.219-228
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• 2009

The growing application and the numerous qualities of induction motors (1M) in industrial processes that require high security and reliability levels has led to the development of multiple methods for early fault detection. However, various faults can occur, such as stator short-circuits and rotor failures. Traditionally the diagnosis machine is done through a sinusoidal power supply, in the present paper we study experimentally the effects of the rotor failures, such as broken rotor bars in function of the ac supplying, the load and show the impact of the converter from diagnosis of the machine. The technique diagnosis used is based on the spectral analysis of stator currents or stator voltages respectively according to the types of induction motor ac supplying. So, four different ac supplying are considered: ${\odot}$ the IM is directly by the balanced three-phase network voltage source, ${\odot}$ the IM is fed by a sinusoidal current source given the controlled by hysteresis, ${\odot}$ the IM is fed (in open loop) by a scalar control imposing through ratio V/f=constant, ${\odot}$ the IM is controlled through a vector control using space vector pulse width modulation (SVPWM) technique inverter with an outer speed loop.

• Journal of Sensor Science and Technology
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• v.23 no.5
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• pp.332-336
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• 2014

In this paper, we propose a complementary metal oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) PMOSFET-type photodetector for high-speed operation. The GBT photodetector of an active pixel sensor (APS) consists of a floating gate ($n^+$-polysilicon) tied to the body (n-well) of the PMOSFET. The p-n junction photodiode that is used in a conventional APS has a good dynamic range but low photosensitivity. On the other hand, a high-gain GBT photodetector has a high level of photosensitivity but a narrow dynamic range. In addition, the pixel size of the GBT photodetector APS is less than that of the conventional photodiode APS because of its use of a PMOSFET-type photodetector, enabling increased image resolution. A CMOS binary image sensor can be designed with simple circuits, as a complex analog to digital converter (ADC) is not required for binary processing. Because of this feature, the binary image sensor has low power consumption and high speed, with the ability to switch back and forth between a binary mode and an analog mode. The proposed CMOS binary image sensor was simulated and designed using a standard CMOS $0.18{\mu}m$ process.

• Journal of Advanced Navigation Technology
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• v.20 no.5
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• pp.482-489
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• 2016

Detection of gamma ray can be available using optical fiber scintillator under radiation environment. It monitors the transfer energies of these ions by photodiodes and then convertes into currents. The module which converts those currents into voltages and processes signals is named fine current module TIA, and it is essentially important to convert currents into voltages with high linearity. We have studied and developed the TIA, improving converting linearity and minimizing noises and off-set voltages. Also, we have made efforts to develop precise and accurate current module in compliance with concerned requirements. First of all, we established developing theory, developed related circuits, and then made the current module. And, we confirmed its stability and linearity to be more excellent than any other equipment proposed by other references. We tested the developed fine current modules in the real radiation environment under authorized supervising, confirmed them to meet related requirements.

• Journal of Advanced Navigation Technology
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• v.20 no.6
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• pp.612-616
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• 2016

Gamma-ray must be detected and processed immedietely after generation of it in the circumstances where it exists. Software methology may be used to process randomly generated signals, but its memory size and processing time become large. By the way, the hardware circuit to detect randomly generated signals is generalized in industrial site, while those circuits are not able to answer to the cases whose amplitude are very small and also speed high. We researched and developed hardware based peak-hold circuit that is able to detect peaks of gamma-ray signals through direct reading out their values by ADC at the time of maximum reaching for the small amplitude and high speed signals, and proposed and estimated its results in this paper. This peak-hold circuit is adequate to use in the radiation circumstances in which the gamma-rays are heavy because its circuit can catch high speed signals efficiently without software signal processing supports.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.198-204
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• 2001

In this paper, a 3V 8-bit 200MSPS CMOS folding / interpolation A/D Converter is proposed. It employs an efficient architecture whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improved SNDR by to be low input frequency, distributed track and hold circuits are included. In order to obtain a high speed and low power operation, further, a novel dynamic latch and digital encoder based on a novel delay error correction are proposed. The chip has been fabricated with a 0.35${\mu}{\textrm}{m}$ 2-poly 3-metal n-well CMOS technology. The effective chip area is 1070${\mu}{\textrm}{m}$$\times$650${\mu}{\textrm}{m}$ and it dissipates about 230mW at 3.3V power supply. The INL is within $\pm$1LSB and DNL is within $\pm$1LSB, respectively. The SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.857-864
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• 2006

This paper describes a design of low-power/small-area arithmetic circuits which are vector processing unit powering nit, divider unit and square-root unit for mobile 3D graphic accelerator. To achieve area-efficient and low-power implementation that is an essential consideration for mobile environment, the fixed-point f[mat of 16.16 is adopted instead of conventional floating-point format. The vector processing unit is designed using redundant binary(RB) arithmetic. As a result, it can operate 30% faster and obtained gate count reduction of 10%, compared to the conventional methods which consist of four multipliers and three adders. The powering nit, divider unit and square-root nit are based on logarithm number system. The binary-to-logarithm converter is designed using combinational logic based on six-region approximation method. So, the powering mit, divider unit and square-root unit reduce gate count when compared with lookup table implementation.