• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.210-220
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• 2008

We review three examples (an on-chip transmission line resonator [1], a phase-locked loop [2], and an analog-to-digital converter [3]) of design tradeoffs which can in fact be circumvented; the key in each case is that the parameters that seem to trade off with each other are actually separated in time or space. This paper is an attempt to present these designs in such a way that this common approach can hopefully be applied to other circuits. We note reader that this paper is not a new contribution, but a review in which we highlight the common theme from our published works [1-3]. We published a similar paper [4], which, however, used only two examples from [1] and [2]. With the newly added content from [3] in the list of our examples, the present paper offers an expanded scope.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.54-61
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• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.6
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• pp.452-458
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• 2019

This study proposes a new test circuit and control method for the submodules of modular multilevel converter (MMC)-based HVDC systems. The test current of conventional submodule test circuits cannot provide the DC offset components or may have some distortion in the linearized current with the DC offset. The proposed scheme can provide not only the DC component but also linearized current without distortion. Therefore, the submodule test current waveform is relatively similar to that of a real submodule consisting of an MMC-based HVDC system. The validity of the proposed circuit and control method is verified through a simulation and experiment.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.4
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• pp.213-218
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• 2017

The DC electrolytic capacitor for DC-link of power converter is widely used in various power electronic circuits and system application. Its functions include, DC Bus voltage stabilization, conduction of ripple current due to switching events, voltage smoothing, etc. Unfortunately, DC electrolytic capacitors are some of the weakest components in power electronics converters. Many papers have proposed different algorithms or diagnosis method to determinate the ESR and tan ${\delta}$ capacitance C for fault alarm system of the electrolytic capacitor. However, both ESR vary with frequency and temperature. Accurate knowledge of both parameters at the capacitors operating conditions is essential to achieve the best reference data of fault alarm. According to parameter analysis, the capacitance increases with temperature and the initial ESR decreases. Higher frequencies make the reference ESR with the initial ESRo value to decrease. Analysis results show that the proposed DC Bus electrolytic capacitor reference ESR model setting technique can be applied to advanced reference signal of capacitor diagnosis systems successfully.

• ETRI Journal
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• v.29 no.4
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• pp.421-429
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• 2007

This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase-locked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 $mm^2$ die using standard 0.18 ${\mu}m$ CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.

• Journal of Electrical Engineering and Technology
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• v.11 no.3
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• pp.629-638
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• 2016

This paper proposes a State-of-Charge (SOC) balancing control of Battery Power Modules (BPMs) for a modularized battery for Electric Vehicles (EVs) without additional balancing circuits. The BPMs are substituted with the single converter in EVs located between the battery and the inverter. The BPM is composed of a two-phase interleaved boost converter with battery modules. The discharge current of each battery module can be controlled individually by using the BPM to achieve a balanced state as well as increased utilization of the battery capacity. Also, an SOC balancing method is proposed to reduce the equalization time, which satisfies the regulation of a constant DC-link voltage and a demand of the output power. The proposed system and the SOC balancing method are verified through simulation and experiment.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.4
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• pp.19-27
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• 2007

This paper presents a novel soft-switching PWM utility frequency AC to high frequency AC power conversion circuit incorporating boost H-bridge inverter topology, which is more suitable and acceptable for cost effective consumer induction heating applications. The operating principle and the operation modes are presented using the switch mode equivalent circuits and the operating voltage and current waveforms. The performances of this high-frequency inverter using the latest IGBTs are illustrated, which includes high frequency power regulation and actual efficiency characteristics based on zero voltage soft-switching(ZVS) operation ranges, and the power dissipation as compared with those of the conventional type high frequency inverter. In addition, a dual mode control scheme of this high frequency inverter based on asymmetrical pulse width modulation(PWM) and pulse density modulation(PDM) control scheme is discussed in this paper in order to extend the soft switching operation ranges and to improve the power conversion efficiency at the low power settings. The power converter practical effectiveness is substantially proved based on experimental results from practical design example.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1317-1319
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• 1997

This paper is to study and develope a measurement apparatus for ferroelectricity. The apparatus consists of wave generation part, high voltage amplifier part, measurement part, data acquisition part and the related controll circuits. Single or double excitation wave is digitalized and sent to the external RAM of wave generation part by personal computer. These datas saved in the RAM are converted to analog excitation wave through D/A converter. The frequency of excitation wave is depend on the read-out speed of the RAM by clock pulse. Such generated wave is applied to high voltage amplifier as a input voltage. The output of high voltage amplifier is applied to ferroelectrics and the response is obtained from the charge amplifier of measurement part. The response is sampled and converted to digital datas through AID converter. These digital datas are automatically saved in the external RAM of acquisition part. The computer takes the digital datas and calculates the electric displacement D, the electric field and the dielectric constant $\varepsilon$. We tested for PZT ceramic sample and could observed the D-E hysteresis lops and ${\varepsilon}_s$-E hysteresis loops with good forms.