• Proceedings of the KIEE Conference
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• 2001.10a
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• pp.301-304
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• 2001

Wind power generation system is one of the most useful energy resource using natural environment. One of the biggest problem we encountered is toot the wind speed is fluctuating sharply according to the weather conditions rather than it is stable. In this paper we do the equivalent modeling the mechanical energy of wind power turbine according to wind speed into the synchronous generator. We analyse the equivalent modeling output part of rectifier into DC/DC converter input part theoretically. We analyse a battery charging characteristics for power storage enabling the supply of stable power to the load. We design a system and do the modeling of it analytically so that it supplies a stable power to the load by constructing a DC-AC inverter point. Also we make a small size model usable in actual wind power generation system of 30kw and make an experiment and confirm its validity.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.1
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• pp.47-52
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• 2002

It was virtually declared that measurement science must abandon the error analysis of measurement when ISO had published "Guide to Expression of uncertainty in Measurement" International inclination of measurement field in order to guarantee the traceability and confidence of measurement results discards the error concept and instead analyzes the measurement uncertainty. In this paper we establish a mathematical model of measurement and analyze all uncertainty factors as possible as for yielding the measurement uncertainty in the course of the calibration of RF multimeter using Transfer Standard, Thermal Voltage Converter We produce the expanded uncertainty by analyzing cable effects, correlation of thermocoupler and DC meter, DC source, RF source, attenuator, reflection coefficients and DUT.s and DUT.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.12 no.1
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• pp.45-50
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• 1998

In recent year, inverters and cycloconverters system are widely used for fed induction motor drives. Motor drives by cycloconverter is possible to frequency have been directly changed without AC/DC converter, so that circuits is simpler than inverter. A aims of this paper is the control strategy and hardware design for vector control system by cycloconverter fed induction motor drives. In this paper, Algorithm of vector control is derivlid from the model of controlled current source-fed induction motor. Vector control system is implemented using these algorithm and a pulse width controled cycloconverter using a SCR. Cycloconverter of vector control system is controlled by pulse width of SCR's trigger signal. pulse width is controlled primary command current $li_1l$ and frequency TEX>$\omega_1$..

• Journal of Power Electronics
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• v.11 no.3
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• pp.311-318
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• 2011

LCL filters installed at converter outputs offer a higher harmonic attenuation than L filters. However, as a three order resonant circuit, it is difficult to stabilize and has a risk of oscillating with the power grid. Therefore, careful design is required to damp LCL resonance. Compared to a passive damping method, an active damping method is a more attractive solution for this problem, since it avoids extra power losses. In this paper, the damping capabilities of capacitor current, capacitor voltage, and grid-side current feedback methods, are analyzed under the discrete-time state-space model. Theoretical analysis shows that the grid-side current feedback method is more suitable for use in active power filters, because it can damp LCL resonance more effectively than the other two methods when the ratio of the resonance and the control frequency is between 0.225 and 0.325. Furthermore, since there is no need for extra sensors for additional states measurements, this method provides a cost-efficient solution. To support the theoretical analysis, the proposed method is tested on a 7-kVA single-phase shunt active power filter.

• Journal of Power Electronics
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• v.18 no.1
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• pp.81-91
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• 2018

This paper proposes a double line voltage synthesis (DLVS) strategy for three-to-five phase direct matrix converters. In the proposed strategy, the input and expected output voltages are divided into 6 segments and 10 segments, respectively. In addition, in order to obtain the maximum voltage transfer ratio (VTR), the input line voltages and "source key" should be selected reasonably according to different combinations of input and output segments. Then, the corresponding duty ratios are calculated to determine the switch sequences in different segment combinations. The output voltages and currents are still sinusoidal and symmetrical with little lower order harmonics under unbalanced or distorted input voltages by using this strategy. In addition, the common mode voltage (CMV) can be suppressed by rearranging some of the switching states. This strategy is analyzed and studied by a simulation model established in MATLAB/Simulink and an experimental platform, which is controlled by a DSP and FPGA. Simulation and experimental results verify the feasibility and validity of the proposed DLVS strategy.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.335-336
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• 2014

This paper investigates the design of coupled inductor for minimum inductor current ripple in rapid traction battery charger systems. Based on the general circuit model of coupled inductor together with the operating principles of dc-dc converter, the relationship between the ripple size of inductor current and the coupling factor is derived under the different duty ratio. The optimal coupling factor which corresponds to a minimum inductor ripple current becomes -1, i.e. a complete inverse coupling without leakage inductance, as the steady-state duty ratio operating point approaches 0.5. In an opposite manner, the optimal coupling factor value of zero, i.e. zero mutual inductance, is required when the steady-state duty ratio operating point approaches either zero or one. Coupled inductors having optimal coupling factor can minimize the ripple current of inductor and battery current resulting in a reliable and efficient operation of battery chargers.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.25-26
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• 2014

배터리를 사용하는 하이브리드 시스템의 확장으로 인하여 2차 전지를 활용할 수 있는 양방향 컨버터의 사용이 증가하고 이에 대한 연구의 필요성 또한 증가하고 있다. 기존 비절연형 단방향 컨버터는 인덕터의 전류와 부하단 캐패시터의 전압을 변수로 지정하고 고정 전원과 고정부하를 대입하여 모델링에 적용했지만, 실제 사용되는 양방향 컨버터의 동작과는 차이가 있다. 또한 이상적인 전원과는 달리 배터리의 단자전압은 SOC 및 충방전 상태에 따라 전압 변동이 일어나고 컨버터의 스위칭 동작에 의해 전압 리플이 발생하기 때문에 제어기를 설계하기 위해서는 이를 반영하여 해석하는 것이 필요하다. 본 논문에서는 비절연형 양방향 컨버터의 양쪽에 부착된 캐패시터가 모두 변수로 적용된 전달함수와 이를 이용하여 설계된 제어기를 제안한다. 컨버터 모델링에 State-Space Averaging 방법을 사용하여 양방향 컨버터의 소신호 분석을 하였고, 충전 모드와 방전 모드 일때 전달함수를 각각 구하였다. 앞서 구한 전달함수를 이용하여 pole/zero 분석을 통해 PI 제어기 설계를 하였고, 주파수 분석을 통해 안정성을 확인하였다.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1469-1479
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• 2017

Primary-side regulation (PSR) scheme is widely applied in low power applications, such as cell phone chargers, network adapters, and LED drivers. However, the efficiency and standby power requirements have been improved to a high standard due to the new trends of DOE (Department Of Energy) Level VI and COC (Code Of Conduct specifications) V5. The major drawbacks of PSR include poor regulation due to inaccurate feedback and difficulty in acquiring acceptable regulation. A novel adaptive blanking strategy for constant current and constant voltage regulation is proposed in this paper. An accurate model for the sample blanking time related to transformer leakage inductance and the metal-oxide-semiconductor field-effect transistor (MOSFET) parasitic capacitance is established. The proposed strategy can achieve accurate detection for ultra-low standby power. In addition, numerous control factors are analyzed in detail to eliminate the influence of leakage inductance on the loop stability. A dedicated controller integrated circuit (IC) with a power MOSFET is fabricated to verify the effectiveness of the proposed control strategy. Experimental results demonstrated that the prototype based on the proposed IC has excellent performance.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1467-1476
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• 2019

Grid unbalanced faults can cause core saturation of power transformer and produce lower-order harmonics. These issues increase the electrical stress of power electronic devices and can cause a tripping of an entire HVDC system. In this paper, based on the positive-sequence and negative-sequence impedance model of a VSC-HVDC system as seen from the point of common connection (PCC), the resonance problem is analyzed and the factors determining the resonant frequency are obtained. Furthermore, to suppress over-voltage and over-current during resonance, a novel method using a virtual harmonic resistor is proposed. The virtual harmonic resistor emulates the role of a resistor connected in series with the commutating inductor without influencing the active and reactive power control. Simulation results in PSCAD/EMTDC show that the proposed control strategy can suppress resonant over-voltage and over-current. In addition, it can be seen that the proposed strategy improves the safety of the VSC-HVDC system under unbalanced faults.

• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.71-76
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• 2021

Digital decimation filters are used in various digital signal processing systems using ADCs, including digital communication systems and sensor network systems. When the sampling rate of digital data is reduced, aliasing occurs. So, an anti-aliasing filter is necessary to suppress aliasing before down-sampling the data. Since the anti-aliasing filter has to have a sharp transition band between the passband and the stopband, the order of the filter is very high. However, as the order of the filter increases, the complexity and area of the filter increase, and more power is consumed. Therefore, in this paper, we propose two types of decimation filters, focusing on reducing the area of the hardware. In both cases, the complexity of the circuit is reduced by applying the required down-sampling rate in two times instead of at once. In addition, CIC decimation filters without a multiplier are used as the decimation filter of the first stage. The second stage is implemented using a CIC filter and a down sampler with an anti-aliasing filter, respectively. It is designed with Verilog-HDL and its function and implementation are validated using ModelSim and Quartus, respectively.