• Title/Summary/Keyword: Conversion speed

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Development of Wind Speed Estimator for Wind Turbine Generation System (풍력발전 시스템을 위한 풍속 추정기 개발)

  • Kim, Byung-Moon;Kim, Sung-Ho;Song, Hwa-Chang
    • Journal of the Korean Institute of Intelligent Systems
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    • v.20 no.5
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    • pp.710-715
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    • 2010
  • As wind has become one of the fastest growing renewable energy sources, the key issue of wind energy conversion systems is how to efficiently operate the wind turbines in a wide range of wind speeds. The wind speed has a huge impact on the dynamic response of wind turbine. For this purpose, many control algorithms are in need for a method to measure wind speed to increase performance. Unfortunately, no accurate measurement of the effective wind speed is online available from direct measurements, which means that it must be estimated in order to make such control methods applicable in practice. In this paper, a new method based on Kalman filter and artificial neural network is presented for the estimation of the effective wind speed. To verify the performance of the proposed scheme, some simulation studies are carried out.

Proposal of Return Period and Basic Wind Speed Map to Estimate Wind Loads for Strength Design in Korea (강도설계용 풍하중 평가를 위한 재현기간과 기본풍속지도의 제안)

  • Ha, Young-Cheol
    • Journal of the Architectural Institute of Korea Structure & Construction
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    • v.34 no.2
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    • pp.29-40
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    • 2018
  • Strength design wind loads for the wind resistance design of structures shall be evaluated by the product of wind loads calculated based on the basic wind speed with 100 years return period and the wind load factor 1.3 specified in the provisions of load combinations in Korean Building Code (KBC) 2016. It may be sure that the wind load factor 1.3 in KBC(2016) had not been determined by probabilistic method or empirical method using meteorological wind speed data in Korea. In this paper, wind load factors were evaluated by probabilistic method and empirical method. The annual maximum 10 minutes mean wind speed data at 69 meteorological stations during past 40 years from 1973 to 2012 were selected for this evaluation. From the comparison of the results of those two method, it can be found that the mean values of wind load factors calculated both probability based method and empirical based method were similar at all meteorological stations. When target level of reliability index is set up 2.5, the mean value of wind load factors for all regions should be presented about 1.35. When target level of reliability index is set up 3.0, wind load factor should be presented about 1.46. By using the relationship between importance factor(conversion factor for return period) and wind load factor, the return periods for strength design were estimated and expected wind speeds of all regions accounting for strength design were proposed. It can be found that return period to estimate wind loads for strength design should be 500 years and 800 years in according to target level of reliability index 2.5 and 3.0, respectively. The 500 years basic wind speed map for strength design was suggested and it can be used with a wind load factor 1.0.

Stand-Alone Pico-Hydro Generation System using a High-Efficiency IPM Synchronous Generator

  • Kurihara, Kazumi;Kubota, Tomotsugu
    • Journal of international Conference on Electrical Machines and Systems
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    • v.3 no.2
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    • pp.121-125
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    • 2014
  • This paper presents a successful stand-alone pico-hydro generation system using a high-efficiency interior permanent-magnet (IPM) synchronous generator. A 1-kW 4-pole V-type IPM generator with low voltage regulation is used for laboratory test in stand-alone hydro energy conversion system. It has been found from experimental results that the constant output voltage is supplied stably by the proposed system under wide speed range.

Design of an 8-bit Color Adjustor for SDTV Using Verilog HDL (Verilog HDL을 이용한 SDTV용 8bit 색상 보정기의 설계)

  • Jeon, Byoung-Woong;Song, In-Chae
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.801-804
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    • 2005
  • In this paper, we designed an 8-bit color adjustor for SDTV using Verilog HDL. The conversion block requires a lot of multiplication. So we adopted Booth algorithm to reduce amount of operation and processing time. To improve speed, we designed the system output as parallel structure. We synthesized the designed system using Xilinx ISE and verified the operation through simulation using Modelsim.

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The analysis of the conversive limitation of electric energy for the gate turn on thyristor inverter (Gate turn on thyristor 역변환장치의 변환전력한계치에 대하여)

  • Hee Yung Chun
    • 전기의세계
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    • v.17 no.2
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    • pp.6-10
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    • 1968
  • The conversive limitation of electric energy for the thyristor inverter is analysed under the boundary conditions which the term of a negative inverse voltage is longer than that of the turn off time of the thyristor under commutation. It is clear that the maximum electric energy conversion is affected by the turn off time of the thyristor, the reactance of a commutation reactor, the capacity of a commutation condenser and the voltage of Direct current source. It is useful for design the thyrister invertor and the motor speed control to apply the above conclusion.

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Fuel stratification by multiple injection in DME HCCI engine combustion (DME 예혼합 압축착화 엔진에서 다단분사를 통한 연료 성층화)

  • Yoon, Hyeonsook;Bae, Choongsik
    • 한국연소학회:학술대회논문집
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    • 2012.11a
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    • pp.311-312
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    • 2012
  • Homogeneous charge compression ignition combustion with multiple-injection strategy using dimethyl-ether was investigated in a single cylinder direct-injection compression-ignition engine. The combustion performance and exhaust emissions were tested by varying the post injection conditions. The experiments were carried out under low load and low speed conditions. By the late post injection near the top dead center, the combustion phase was retarded and lengthened, and the fuel conversion efficiencies improved without the drawbacks of exhaust emissions increment.

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Software Defined Radio를 위한 AD/DA 변환기의 기술 동향

  • 신원화;한건희
    • The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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    • v.10 no.3
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    • pp.39-47
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    • 1999
  • This paper presents the survey of technical trend in AD converters for wireless communication systems. This paper provides explanations about the performance measure of ADC in wireless communication application and the relation ship between BER versus effective resolution and sampling speed. The survey suggests that at least one step analog frequency down conversion is required for software defined radio systems due to current technological limit.

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Real time analysis of multichannel EEG signal (다중채널 EEG 신호의 실시간 해석에 관한 연구)

  • 조재희;장태규;양원영
    • 제어로봇시스템학회:학술대회논문집
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    • 1992.10a
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    • pp.829-833
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    • 1992
  • This paper presents the design of an automated EEG analyzing system. The design considerations including processing speed, A/D conversion, filtering, and waveforms detection, are overviewed with the description of the associated EEG characteristics. The architecture of the currently implemented system consists of a p-controller based front-end signal processing unit and a host computer system. The data acquisition procedures are described along with a couple of illustrations of the acquired EEG/EOG signal.

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비트-슬라이스 마이크로프로세서를 이용한 LOG PCM/ADPCM 부호변환시스템 설계

  • Jo, Jeong-Yeon;Lee, Yeong-Ho
    • ETRI Journal
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    • v.6 no.3
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    • pp.9-16
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    • 1984
  • This paper describes $\mu$-law PCM/ADPCM Code Conversion System. The system algorithm is computer-simulated, and with the result of simulation the system is designed by using the Am 2900 family's Bit-Slice Microprocessors which have a high-speed processing power. The ADPCM algorithm is based on Jayant's model and the converting algorithm between $\mu$-law PCM and linear PCM is developed according to the CCITT Recommendation G. 711.

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A Novel Frequency-to-Digital Converter Using Pulse-Shrinking

  • Park, Jin-Ho
    • KIEE International Transactions on Electrophysics and Applications
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    • v.3C no.6
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    • pp.220-223
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    • 2003
  • In this paper, a new frequency-to-digital converter without an analog element is proposed. The proposed circuit consists of pulse-shrinking elements, latches and D flip-flops, and the operation is based on frequency comparison by the pulse-shrinking element. In the proposed circuit, the resolution of digital output can be easily improved by increasing the number of the pulse-shrinking elements. The FDC performance is improved in viewpoints of operating speed and chip area. In designed FDC, error of frequency-to-digital conversion is less than 0.1 %.