• Journal of KIISE:Computer Systems and Theory
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• v.29 no.12
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• pp.655-664
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• 2002

In many data-parallel applications massive parallelism can be easily extracted through data distribution. But it often causes very long communication latency. This paper shows that task parallelism, which is extracted from data-parallel programs, can be exploited to hide such communication latency Unlike the most previous researches over exploitation of task parallelism which has not been considered together with data parallelism, this paper describes exploitation of task parallelism in the context of data parallelism. PCFG(Parallel Control Flow Graph) is proposed to represent a multithreaded program consisting of a few task threads each of which can include a few data-parallel loops. It is also described how a PCFG is constructed from a source data-parallel program through HDG(Hierarchical Dependence Graph) and how the multithreaded program can be constructed from the PCFG.

• Journal of KIISE:Software and Applications
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• v.31 no.5
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• pp.643-650
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• 2004

Control flow graph is used for Performing many Program-analysis techniques, such as data-flow and control-dependence analysis, and software-engineering techniques, such as program slicing and testings. For these analyses to be safe and useful, the CFG should incorporate the exception flows that are induced by exceptions. In previous research to construct control flow graph, normal flows and exception flows are computed at the same time, since these two flows are known to be mutually dependent. By investigating realistic Java programs, we found that the cases when these two flows are mutually dependent rarely happen. So, we can decouple exception flow analysis from normal flow analysis. In this paper we propose an analysis that estimates exception flows. We also propose exception flow graph to represent exception flows. And we show that the control flow graph that accounts for exception flows can be constructed by merging exception flow graph onto normal control flow graph.

• Journal of the Korea Society of Computer and Information
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• v.18 no.7
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• pp.111-123
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• 2013

To verify software vulnerability, the method of conjecturing software structure and then testing the software based on the conjectured structure has been highlighted. To utilize the method, an efficient way to conjecture software structure is required. The popular graph and tree methods such as DFG(Data Flow Graph), CFG(Control Flow Graph) and CFA(Control Flow Automata) have a serious drawback. That is, they cannot express software in a hierarchical fashion. In this paper, we propose a method to overcome the drawback. The proposed method applies various input data to a binary code, generate CFG's based on the code output and construct a HCFG (Hierarchical Control Flow Graph) to express the generated CFG's in a hierarchical structure. The components required for HCFG and progressive algorithm to construct HCFG are also proposed. The proposed method is verified through constructing the software architecture of an open SMTP(Simple Mail Transfer Protocol) server program. The structure generated by the proposed method and the real program structure are compared and analyzed.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.11
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• pp.876-880
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• 2009

A control flow graph(CFG) is an essential data structure for program analyses based on graph theory or control-/data- flow analyses. Esterel is an imperative synchronous language and its synchronous parallelism makes it difficult to construct a CFG of an Esterel program. In this work, we present a method to construct over-approximated CFGs for Esterel. Our method is very intuitive and generated CFGs include not only exposed paths but also invisible ones. Though the CFGs may contain some inexecutable paths due to complex combinations of parallelism and exception handling, they are very useful for other program analyses.

• The Journal of the Korea Contents Association
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• v.6 no.1
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• pp.160-169
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• 2006

This paper describes the data structure for program analysis and optimization of bytecode level. First we create an extended CFG(Control Flow Graph). Because of the special properties of bytecode, we must adaptively extend the existing control flow analysis techniques. We build basic blocks to create the CFG and create various data that can be used for optimization. The created CFG can be tested for comprehension and maintenance of Java bytecode, and can also be used for other analyses such as data flow analysis. This paper implements CTOC's CTOC-BR(CTOC-Bytecode tRanslator) for control flow analysis of bytecode level. CTOC(Classes To Optimized Classes) is a Java bytecode framework for optimization and analysis. This paper covers the first part of the CTOC framework. CTOC-BR is a tool that converts the bytecode into tree form for easy optimization and analysis of bytecode in CTOC.

• Annual Conference of KIPS
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• 2019.10a
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• pp.475-478
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• 2019

웹어플리케이션의 발전에 따라 자바스크립트 런타임 플랫폼인 Node.js 의 사용도 증가하고 있다. 개발자들은 Node.js 의 다양한 모듈을 활용하여 프로그래밍을 하게 되는데, Node.js 모듈 보안의 중요성에 비하여 모듈 취약점 분석은 충분히 이루어지지 않고 있다. 본 논문에서는 소스코드의 구조를 트리 형태로 표현하는 Abstract Syntax Tree 와 소스코드의 실행 흐름 및 변수의 흐름을 그래프로 나타내는 Control Flow Graph/Data Flow Graph 가 Node.js 모듈 취약점 분석에 효율적으로 활용될 수 있음을 서술하고자 한다. Node.js 모듈은 여러 스크립트 파일로 나누어져 있다는 점과 사용자의 입력이 분명하다는 특징이 있다. 또한 자바스크립트 언어를 사용하므로 선언된 변수들의 타입에 따라 적용되는 범위인 scope 가 다르게 적용된다는 특징이 있다. 본 논문에서는 이러한 Node.js 모듈의 특징을 고려하여 Abstract Syntax Tree 및 Control Flow Graph/Data Flow Graph 을 어떻게 생성하고 취약점 분석에 활용할 것인지에 대한 방법론을 제안하고, 실제 분석에 활용할 수 있는 코드 구현을 통하여 구체화시키고자 한다.

• The Transactions of the Korea Information Processing Society
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• v.6 no.6
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• pp.1646-1655
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• 1999

This thesis presents a new VHDL intermediate format CDDG(Control Dominated Data Graph) and a minimal constrained scheduling algorithm for an optimal control dominated ASIC design. CDDG is a control flow graph which represents conditional branches and loops efficiently. Also it represents data dependency and such constraints as hardware resource and timing. In the proposed scheduling algorithm, the constraints using the inclusion and overlap relation among subgraphs. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.

• Journal of the Korea Society of Computer and Information
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• v.13 no.1
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• pp.153-160
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• 2008

This paper shows the maximum data flow utilizing the Weight Bipartite Graph Matching system. The Weight Bipartite Graph Matching system sets the data transmission as edges and guides the maximum data flow on the set server and the client. The proposed Weight Bipartite Graph Matching system implements the multi-user interface video conference system. By sending max data to the server and having the client receive the max data, the non-continuance of the motion image frame, the bottleneck phenomenon, and the broken images are prevented due to the excellent capacity. The experiment shows a two-times better excellency than that of the previous flow control.

• The KIPS Transactions:PartD
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• v.8D no.3
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• pp.257-264
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• 2001

We developed a SIFG (Slice-based Information Graph), which modelled the information flow on program on the basis of the information flow of data tokens on data slices. Then we defied a SCM (Slice-based complexity measure), which measured the program complexity by measuring the complexity of information flow on SIFG. SCM satisfied the necessary properties for complexity measure proposed by Briand et al. SCM could measure not only the control and data flow on program but also the physical size of program unlike the existing measures.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.196-204
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• 1996

This paper presents a new scheduling algorithm, which is the most improtant subtask in the high level synthesis. The proposed algorithm performs scheduling in consideration of resource sharing concept based on characteristics of conditionsla bransches in the intermediate data structure. CDFG (control data flow graph) generated by a VHDL analyzer. This algorithm constructs a conditon graph based on time frame of each operation using both the ASAP and the ALAP scheduling algorithm. The conditon priority is obtained from the condition graph constructed from each conditional brance. The determined condition priority implies the sequential order of transforming the CDFG with conditonal branches into the CDFG without conditional branches. To minimize resource cost, the CDFG with conditional branches are transformed into the CDFG without conditonal brancehs according to the condition priority. Considering the data dependency, the hardware constraints, and the data execution time constraints, each operation in the transformed CDFG is assigned ot control steps. Such assigning of unscheduled operations into contorl steps implies the performance of the scheduling in the consecutive movement of operations. The effectiveness of this algorithm is hsown by the experiment for the benchmark circuits.