• Title/Summary/Keyword: Connection scheduler

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Reducing the Flow Completion Time for Multipath TCP

  • Heo, GeonYeong;Yoo, Joon
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.13 no.8
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    • pp.3900-3916
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    • 2019
  • The modern mobile devices are typically equipped with multiple network interfaces, e.g., 4G LTE, Wi-Fi, Bluetooth, but the current implementation of TCP can support only a single path at the same time. The Multipath TCP (MPTCP) leverages the multipath feature and provides (i) robust connection by utilizing another interface if the current connection is lost and (ii) higher throughput than single path TCP by simultaneously leveraging multiple network paths. However, if the performance between the multiple paths are significantly diverse, the receiver may have to wait for packets from the slower path, causing reordering and buffering problems. To solve this problem, previous MPTCP schedulers mainly focused on predicting the latency of the path beforehand. Recent studies, however, have shown that the path latency varies by a large margin over time, thus the MPTCP scheduler may wrongly predict the path latency, causing performance degradation. In this paper, we propose a new MPTCP scheduler called, choose fastest subflow (CFS) scheduler to solve this problem. Rather than predicting the path latency, CFS utilizes the characteristics of these paths to reduce the overall flow completion time by redundantly sending the last part of the flow to both paths. We compare the performance through real testbed experiments that implements CFS. The experimental results on both synthetic packet generation and actual Web page requests, show that CFS consistently outperforms the previous proposals in all cases.

Development of a Power Plant Simulation Tool with GUI based on General Purpose Design Software

  • Kim Dong Wook;Youn Cheong;Cho Byung-Hak;Son Gihun
    • International Journal of Control, Automation, and Systems
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    • v.3 no.3
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    • pp.493-501
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    • 2005
  • A power plant simulation tool ('PowerSim') has been developed with 10 years experience from the development of a plant simulator for efficient modeling of a power plant. PowerSim is the first developed tool in Korea for plant simulation with various plant component models, instructor station function and the Graphic Model Builder (GMB). PowerSim is composed of a graphic editor using general purpose design software, a netlist converter, component models, the scheduler, Instructor Station and an executive. The graphic editor generates a netlist that shows the connection status of the various plant components from the Simdiagram, which is drawn by Icon Drag method supported by GUI environment of the PowerSim. Netlist Converter normalizes the connection status of the components. Scheduler makes scheduling for the execution of the device models according to the netlist. Therefore, the user makes Simdiagram based on the plant Pipe and Instrument Drawing (P&ID) and inputs the plant data for automatic simulating execution. This paper introduces Graphic Model Builder (GMB), instructor station, executive and the detailed introduction of thermal-hydraulic modeling. This paper will also introduce basic ideas on how the simulation Diagram, based on netlist generated from general purpose design software, is made and how the system is organized. The developed tool has been verified through the simulation of a real power plant.

The ATM SAR Processor Optimized for VoDSL Service (VoDSL 서비스에 최적화된 ATM SAR 프로세서)

  • 손윤식;정정화
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.10
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    • pp.9-16
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    • 2003
  • In this paper, we propose an ATM processor suitable for VoDSL subscriber's equipments. The processor is composed of ATM block, AAL protocol block and ATS scheduler, and provides up to 4 VCC which service data and voice traffics on the ATM network. The proposed ATS scheduler can guarantee QoS of the voice traffic and supports multiple AAL2 packet. The ATM processor is manufactured on the 0.35 micron fabrication line of HYNIX semiconductor and provides the maximum data transfer rate of up to 52 Mbps. We implement the LAD, which is the VoDSL subscriber's equipment. The experimental results on the test bed network shows that the proposed hardware scheme successfully services most of the applications of the VoDSL services.

A Medium Access Control Protocol for rt- VBR Traffic in Wireless ATM Networks

  • Lim, In-Taek
    • Journal of information and communication convergence engineering
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    • v.5 no.1
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    • pp.29-34
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    • 2007
  • This paper proposes a MAC protocol for real-time VBR (rt-VBR) services in wireless ATM networks. The proposed protocol is characterized by a contention-based mechanism of the reservation request, a contention-free polling scheme for transferring the dynamic parameters, and a priority scheme of the slot allocation. The design objective of the proposed protocol is to guarantee the real-time constraint of rt-VBR traffic. The scheduling algorithm uses a priority scheme based on the maximum cell transfer delay parameter. The wireless terminal establishes an rt-VBR connection to the base station with a contention-based scheme. The base station scheduler allocates a dynamic parameter minislot to the wireless terminal for transferring the residual lifetime and the number of requesting slots as the dynamic parameters. Based on the received dynamic parameters, the scheduler allocates the uplink slots to the wireless terminal with the most stringent delay requirement. The simulation results show that the proposed protocol can guarantee the delay constraint of rt-VBR services along with its cell loss rate significantly reduced.

Study on Improvement of UBR Traffic Performance using ABT Block Scheduling in Multicast ATM Networks (멀티캐스트 ATM망에서 ABT 블록스케쥴링을 이용한 UBR 트래픽 성능 개선에 관한 연구)

  • 임동규
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.10B
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    • pp.1665-1674
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    • 2000
  • This paper treats the interworking of LAN-based networks like TCP over the ATM protocol stack in an ATM multicast session. Multicast connection will cause CIP since multicast group members form a connection tree by some tree methods and share the connected tree. The paper solve the CIP problem through a block-by-block transmission using ABT/IT method. ABT/IT RM cell is modified and block scheduling algorithm considering the traffic types is applied to each ATM switch using the enhanced RM cell. Block scheduling algorithm will avoid the indiscriminate discard of UBR traffic when congestion occurs and it can provide an efficient and fair service. The paper builds a block scheduler system and suggests the block scheduling algorithm for a multicast session in an ATM switch. UBR traffics arriving at the switch trough each VC is classified by the traffic type and stored at class buffer and thereafter indisciminately transmitted. When block scheduling algorithm is applied it will improve the UBR traffic performance such as end-to-end delay cell block loss ration etc. This paper evaluated the performance of block scheduling algorithm through the simulation using the C language and data structure.

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Development of Vessel Communication System for Integrated Management and Inter-exchange of Maritime Data (해상 데이터 통합 관리 및 상호교환을 위한 선박 통신 시스템 개발)

  • Kang, Nam-seon;Kim, Ji-goo;Lee, Seon-ho
    • Journal of Advanced Navigation Technology
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    • v.19 no.5
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    • pp.354-362
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    • 2015
  • In this study, for integrated management and inter-exchange of operational data generated by ships and land-side information on safe and business, a vessel communication system with modular functions was designed that applied high efficiency compression, least-cost algorithms and Inmarsat FBB connection automation system. Performance test at the KTsat Kumsan satellite earth station; system was found to delivered an average transfer speed of 7 kB/S, which was significant improvement from the existing commercial product's average speed of 5 kB/S. It also delivered twice the efficiency of the existing product in terms of compression rate and transfer of the most widely used office files in maritime businesses.

An Efficient Algorithm for Finding the Earliest Available Interval on Connection-Oriented Networks (연결 지향 네트워크에서 최초 가용 구간을 찾는 효율적인 알고리즘)

  • Chong, Kyun-Rak
    • Journal of the Korea Society of Computer and Information
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    • v.15 no.3
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    • pp.73-80
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    • 2010
  • The advancement of communication and networking technologies has enabled e-science and commercial application that often require the transport of large volume of data over wide-area network. Schedulable high-bandwidth low-latency connectivity is required to transport the large volume of data. But the public Internet does not provide predictable service performance. Especially, if data providers and users are far away, dedicated bandwidth channels are needed to support remote process efficiently. Currently several network research projects are in progress to develop dedicated connectionsy sA bandwidth scheduler computes an user requested path based on network topology information and link bandwidth allocationsy In this paper, we have proposed an efficient algorithm for finding the earliest time interval when minimum bandwidth and duration are giveny Our algorithm is experimentally compared with the known algorithm.

TCP-aware Segment Scheduling Method for HTTP Adaptive Streaming (HTTP 적응적 스트리밍을 위한 TCP 인지형 세그먼트 스케줄링 기법)

  • Park, Jiwoo;Chung, Kwangsue
    • Journal of KIISE
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    • v.43 no.7
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    • pp.827-833
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    • 2016
  • HTTP Adaptive Streaming (HAS) is a technique that adapts its video quality to network conditions for providing Quality of Experience. In the HAS approach, a video content is encoded at multiple bitrates and the encoded video content is divided into several video segments. A HAS player estimates the network bandwidth and adjusts the video bitrate based on estimated bandwidth. However, the segment scheduler in the conventional HAS player requests video segments periodically without considering TCP. If the waiting duration for the next segment request is quite long, the TCP connection can be initialized and it restarts slow-start. Slow-start causes the reduction in TCP throughput and consequentially leads to low-quality video streaming. In this study, we propose a TCP-aware segment scheduling scheme to improve performance of HAS service. The proposed scheme adjusts request time for the next video request to prevent initialization of TCP connection and also considers the point of scheduling time. The simulation proves that our scheme improves the Quality of Service of the HAS service without buffer underflow issue.

A Real-Time Performance Enhancement Scheme for Ethernet-based DAVIC Residential Network (이더네트 기반 DAVIC 주거망에서의 실시간 성능향상 기법)

  • Lee, Jung-Hoon;Kim, Sung-Baik;Kim, Tae-Woong
    • Journal of KIISE:Information Networking
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    • v.27 no.2
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    • pp.197-205
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    • 2000
  • This paper proposes and evaluates a scheme which enhances real-time performance on the Ethernet-based residential network where cable length is very short and most of traffic passes through a specific device. The scheme aims at enhancing deadline meet ratio of the real-time traffic, for example, video stream by means of applying the functionalities such as queue discrimination and early packet discard as well as maintaining network load properly. The design includes the description on hardware interfaces along with the software modules such as scheduler, device driver and connection manager. The simulation results via SMPL suggest that the proposed network can be used as a cost-effective residential network. We also measure the permissible bandwidth for non-real-time traffic without degrading the performance of real-time traffic.

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A Modular On-the-fly Round Key Generator for AES Cryptographic Processor (AES 암호 프로세서용 모듈화된 라운드 키 생성기)

  • Choi Byeong-Yoon;Lee Jong-Hyoung
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.5
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    • pp.1082-1088
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    • 2005
  • Generating fast round key in AES Rijndael algorithm using three key sizes, such as 128, 192, and 256-bit keys is a critical factor to develop high throughput AES processors. In this paper, we propose on-the-fly round key generator which is applicable to the pipelined and non-pipelined AES processor in which cipher and decipher nodes must be implemented on a chip. The proposed round key generator has modular and area-and-time efficient structure implemented with simple connection of two key expander modules, such as key_exp_m and key_exp_s module. The round key generator for non-pipelined AES processor with support of three key lengths and cipher/decipher modes has about 7.8-ns delay time under 0.25um 2.5V CMOS standard cell library and consists of about 17,700 gates.