• ETRI Journal
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• v.31 no.6
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• pp.809-811
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• 2009

We propose a novel simulation method for modeling the game of golf using SystemC, a system description language that allows modeling of a concurrent system's behavior. Utilizing the proposed simulator, we compare different outing formats of golf, namely, regular and shotgun, in terms of playing time. Our simulation results reveal that the shotgun format can take longer than the regular format if the number of groups in a golf course exceeds 33 for the scenario we tested, confirming the belief that the shotgun format can take longer than the regular format. We also justify our simulation by comparing the simulation and analytical results.

• International conference on construction engineering and project management
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• 2009.05a
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• pp.1540-1547
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• 2009

Steel frame factories were surveyed in this study in order to explore the possibility of shortening the construction time and save on construction cost through overlapping at the stages of design or construction. In the survey, construction professionals were interviewed in order to collect quantitative data. Hypotheses were then formulated, and the data was thereby analyzed using the simulation technique in order to analyze the effects of the concurrent engineering method on shorter construction time and cost saving. In addition, actual cases were analyzed to determine the overlapping rates of major processes in terms of shorter construction time and cost saving and to analyze the relationship between time and cost due to overlapping.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.3
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• pp.778-798
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• 2014

This paper proposes a novel exposed-terminal-eliminated medium access control (ETE-MAC) protocol by combining channel reservation, collision avoidance and concurrent transmissions to improve multi-access performance of the multihop wireless networks. Based on the proposed slot scheduling scheme, each node senses the control channel (CCH) or the data channel (DCH) to accurately determine whether it can send or receive the corresponding packets without collisions. Slot reservation on the CCH can be simultaneously executed with data packet transmissions on the DCH. Therefore, it resolves the hidden-terminal type and the exposed-terminal type problems efficiently, and obtains more spatial reuse of channel resources. Concurrent packet transmissions without extra network overheads are maximized. An analytical model combining Markov model and M/G/1 queuing theory is proposed to analyze its performance. The performance comparison between analysis and simulation shows that the analytical model is highly accurate. Finally, simulation results show that, the proposed protocol obviously outperforms the link-directionality-based dual-channel MAC protocol (DCP) and WiFlex in terms of the network throughput and the average packet delay.

• Journal of Biosystems Engineering
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• v.13 no.3
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• pp.59-70
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• 1988

A computer simulation model for rice circulating concurrent-flow dryer was developed and verified by conduction a series of pilot-scale experiment. The effects of design parameter and operating conditions on dryer performance were analyzed by using simulation. The results indicated that the developed model was found suitable for analyzing operating characteristics. The other results from simulation also showed that; 1) an increse in the initial moisture content resulted in an increase in the drying rate and a reduction in the grain temperature and total energy requirements. 2) an increase in the drying air temperature resulted in an increase in the drying rate and grain temperature. 3) an increase in air flow rate resulted in an radical increase in drying rate, fan power requirements and total energy requirements but an radical decrease in final head rice yield. 4) an increase in the bed depth resulted in an increase in fan power requirements and a lowering of the final head rice yield.

• The KIPS Transactions:PartA
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• v.17A no.2
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• pp.73-80
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• 2010

As the power of hardware has improved, there have been numerous researches in processing concurrently using multitasking method. The incremental evaluation is the evaluation method of reevaluating only affected parts instead of reevaluating overall program when the program has been changed. It is necessary to do more studies that improve the efficiency of concurrent incremental evaluation to do multitasking using multi-threading of Java not to do in parallel using multiprocessor. In this paper, the dependency in the dependency chart is based on the attribute that describes the real value of the variable that directly affects the semantics, thereby doing efficient evaluation. So using the dependency, this paper presents the concurrent incremental evaluation algorithm for Java Languages and proves its correctness, analyzing the efficiency of concurrent incremental evaluation by the simulation.

• Korean Journal of Computational Design and Engineering
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• v.13 no.1
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• pp.36-44
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• 2008

This paper proposes a modeling and simulation process of a panel production line (PPL) in a shipyard. The panel production line is an assembly process to produce a main panel of a flat block and a curved block. In this paper, its activity analysis is carried out using expression of IDEF0, and its process is qualitatively and quantitatively analyzed and modeled by Petri Nets. A commercial discrete event simulation tool, $QUEST^{TM}$, is used for virtual PPL and simulation. The modeling results by Petri Net are mapped to elements of the simulation tool. Finally, an integrated simulation environment of PPL is implemented in order to efficiently utilize the virtual PPL model. With the help of IDEF0 and Petri Nets, we could systematically analyze and describe the PPL process that are characterized as being concurrent, asynchronous, distributed, parallel, nondeterministic, and/or stochastic. Also, the dynamic and concurrent activities of a PPL system were able to be simulated. A timing concept can be included into the Petri nets model to evaluate performance and dependability issues of the system.

• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2989-2996
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• 1998

As the circuit density of VLSI grows and its performance improves, delay fault testing of VLSI becomes very important. Delay faults in a circuit can be categorized into two classes, gate delay faults and path delay faults. This paper proposed two methods in dynamic memory usage in the path delay fault simulation. The first method is similar to that used in concurrent fault simulation for stuck-at faults and the second method reduces dynamic memory usage by not inserting a fault descriptor into the fault list when its value is X. The second method, called Implicit-X method, showed superior performance in both dynamic memory usage and simulation time than the first method, called Concurrent-Simulation-Like method.

• Proceedings of the Korea Society for Simulation Conference
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• 1998.10a
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• pp.137-141
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• 1998

본 연구는 TPN unfolding을 이용하여 WIP의 FMS(Flexible Manufacturing System)를 분석하는 방법을 제시한다. PN의 unfolding은 상태폭발이 발생하지 않는 concurrent system의 검증에 사용되는 순서기반방법이다. 본 연구는 일반적으로 발생하는 순환상태스케쥴문제에서 가장 그 작업과정 시간을 최적화함을 위하여 원래의 net을 동일한 비순환 net으로 바꾸어 줄 수 있는 unfolding 개념을 기반으로 한 것이다.

• Journal of the military operations research society of Korea
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• v.25 no.1
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• pp.199-214
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• 1999

The Constructive Battle Simulation Model is very important to the recent military training for the substitution of the field training. However, real battlefield systems operate under real-time conditions, they are inherently distributed, concurrent and dynamic. In order to reflect these properties by the computer-based simulation systems which represent real world processes, we have been developing constructive simulation model for several years. Conventionally, scheduling and resource allocation activities which have timing constraints, we elaborated on these issues and developed the simulation system on commercially available hardware and operating system with lock-free resource allocation scheme and rate monotonic scheduling.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.761-767
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• 2007

In this paper, we deal wih a concurrent dual band low noise amplifier for a Radio Frequency Identification(RFID) reader operating at 912MHz and 2.45GHz. The design of the low noise amplifier is based on the TSMC $0.18{\mu}m$ CMOS technology. The chip size is $1.8mm\times1.8mm$. To improve the noise figure of the circuit, SMD components and a bonding wire inductor are applied to input matching. Simulation results show that the 521 parameter is 11.41dB and 9.98dB at 912MHz and 2.45GHz, respectively The noise figure is also determined to 1.25dB and 3.08dB at the same frequencies with a power consumption of 8.95mW.