• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.26-34
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• 1999

According to increase of nonlinear power electronics equipment, active power filters have been researched and developed for many years to compensate harmonic disturbances and reactive power. However the commercial of active power filter is being proceeded slowly, because the cost of active power filter compared to the passive filter for harmonic and reactive power compensation is expensive. Especially, the use of DSP (Digital Signal Processing) chip, which is frequently used to control 3-phase active power filter, is a factor of increasing the cost of active power filters. On the other hand, the use of only analog controller makes the controller's circuits much more complicate and depreciates the flexibilities of controller. In this paper, a controller with low cost for 5[kVA] 3-phase active power filter system is designed. To reduce the expense of active filter system, the presented controller is composed of digital control part using Intel 80C196KC $\mu$P and analog control part using hysteresis controller for current control. Characteristic analysis of designed controller for active filter system is performed by computer simulation and compensating characteristics of the designed controller are verified by experiment.tegy can apply to the vector control, leading to better output torque capability in the ac motor drive system. This strategy is that in the overmodulation range, the d-axis output current is given a priority to regulate the flux well, instead the q-axis output curent is sacrificed. Therefore, the vector control even in the overmodulation PWM operation can be achieved well. For this purpose, the d-axis output voltage of a current controller to control the flux is conserved. the q-axis output voltage to control the torque is controlled to place the reference voltage vector on the hexagon boundary in case of the overmodulation. The validity of the proposed overall scheme is confirmed by simulation and experiments for a 22[kW] induction motor drive system.

• KIPS Transactions on Software and Data Engineering
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• v.6 no.2
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• pp.103-116
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• 2017

In this paper, we present the design and implementation of a large-scale qualitative spatial reasoner, which can derive new qualitative spatial knowledge representing both topological and directional relationships between two arbitrary spatial objects in efficient way using Aparch Spark SQL. Apache Spark SQL is well known as a distributed parallel programming environment which provides both efficient join operations and query processing functions over a variety of data in Hadoop cluster computer systems. In our spatial reasoner, the overall reasoning process is divided into 6 jobs such as knowledge encoding, inverse reasoning, equal reasoning, transitive reasoning, relation refining, knowledge decoding, and then the execution order over the reasoning jobs is determined in consideration of both logical causal relationships and computational efficiency. The knowledge encoding job reduces the size of knowledge base to reason over by transforming the input knowledge of XML/RDF form into one of more precise form. Repeat of the transitive reasoning job and the relation refining job usually consumes most of computational time and storage for the overall reasoning process. In order to improve the jobs, our reasoner finds out the minimal disjunctive relations for qualitative spatial reasoning, and then, based upon them, it not only reduces the composition table to be used for the transitive reasoning job, but also optimizes the relation refining job. Through experiments using a large-scale benchmarking spatial knowledge base, the proposed reasoner showed high performance and scalability.

• Journal of KIISE:Software and Applications
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• v.31 no.11
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• pp.1543-1550
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• 2004

Modeling from images is a cost-effective means of obtaining 3D geometric models. These models can be effectively constructed from classical Structure from Motion algorithm. However, it's too difficult to reconstruct whole scenes using SFM method since general sites contain a very complex shapes and brilliant colours. To overcome this difficulty, the current paper proposes a new reconstruction method based on a moving Planar mirror. We devise the mirror posture instead of scene itself as a cue for reconstructing the geometry That implies that the geometric cues are inserted into the scene by compulsion. With this method, we can obtain the geometric details regardless of the scene complexity. For this purpose, we first capture image sequences through the moving mirror containing the interested scene, and then calibrate the camera through the mirror's posture. Since the calibration results are still inaccurate due to the detection error, the camera pose is revised using frame-correspondence of the comer points that are easily obtained using the initial camera posture. Finally, 3D information is computed from a set of calibrated image sequences. We validate our approach with a set of experiments on some complex objects.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.1
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• pp.18-29
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• 2008

NAND Flash memory has been growing popular storage device for the last years because of its low power consumption, fast access speed, shock resistance and light weight properties. However, it has the distinct characteristics such as erase-before-write architecture, asymmetric read/write/erase speed, and the limitation on the number of erasure per block. Due to these limitations, various Flash Translation Layers (FTLs) have been proposed to effectively use NAND flash memory. The systems that adopted the conventional FTL may result in severe performance degradation by the hot data which are frequently requested data for overwrite in the same logical address. In this paper, we propose a novel FTL algorithm called Adaptive Flash Translation Layer (AFTL) which uses sector mapping method for hot data and log-based block mapping method for cold data. Our system removes the redundant write operations and the erase operations by the separating hot data from cold data. Moreover, the read performance is enhanced according to sector translation that tends to use a few read operations. A series of experiments was organized to inspect the performance of the proposed method, and they show very impressive results.

• Applied Chemistry for Engineering
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• v.9 no.7
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• pp.1070-1078
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• 1998

Thermodynamic analysis on carbon dioxide reforming of methane was performed using a computer program which can handle condensed species in the products, and the reforming experiments were conducted over $Al_2O_3$, $La_2O_3$, ZSM-5, MCM-41, KIT-1 supported nickel catalysts, and a commercial ICI 46-1. It was estabished that a system which consists of $CH_4$, $CO_2$, CO, $H_2$, $H_2O$, and C is appropriate for theoretical equilibrium calculations and addition of water vapor or oxygen was found to diminish the contribution of carbon dioxide in reforming. Silicate molecular sieve-supported catalysts such as Ni/ZSM-5, Ni/MCM-41, Ni/KIT-1 were effective for high $CH_4$ and $CO_2$ conversions as well as for high CO yield. Coke formation was suppressed when CaO was added as a promoter. Ni/Ca/KIT-1 which contains 10% Ni with 3% Ca showed conversion approaching equilibrium levels above $650^{\circ}C$ and maintained constant activity over 20 h. Despite increased space velocity, relatively high conversion and CO yield were observed.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.5
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• pp.199-212
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• 2008

Software simulation has been widely used for the design and application development of a large-scale wireless sensor network. The degree of details of the simulation must be high to verify the behavior of the network and to estimate its execution time and power consumption of an application program as accurately as possible. But, as the degree of details becomes higher, the simulation time increases. Moreover, as the number of sensor nodes increases, the time tends to be extremely long. We propose an optimal-synchronous parallel discrete-event simulation method to shorten the time in a large-scale sensor network simulation. In this method, sensor nodes are partitioned into subsets, and each PC that is interconnected with others through a network is in charge of simulating one of the subsets. Results of experiments using the parallel simulator developed in this study show that, in the case of the large number of sensor nodes, the speedup tends to approach the square of the number of PCs participating in the simulation. In such a case, the ratio of the overhead due to parallel simulation to the total simulation time is so small that it can be ignored. Therefore, as long as PCs are available, the number of sensor nodes to be simulated is not limited. In addition, our parallel simulation environment can be constructed easily at the low cost because PCs interconnected through LAN are used without change.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.5
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• pp.451-457
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• 2020

Format recognition and OCR techniques are widely used as methods for detecting and protecting personal information from electronic documents. However, due to the poor recognition rate of the OCR engine, personal information cannot be detected or false positives commonly occur. It also takes a long time to analyze a large amount of electronic documents. In this paper, we propose a method to improve the speed of image analysis of electronic documents, character recognition rate of the OCR engine, and detection rate of personal information by improving the existing method. The analysis speed was increased using the format recognition method while the analysis speed and character recognition rate of the OCR engine was improved by image correction. An algorithm for analyzing personal information from images was proposed to increase the reconnaissance rate of personal information. Through the experiments, 1755 image format recognition samples were analyzed in an average time of 0.24 seconds, which was 0.5 seconds higher than the conventional PAID system format recognition method, and the image recognition rate was 99%. The proposed method in this paper can be used in various fields such as public, telecommunications, finance, tourism, and security as a system to protect personal information in electronic documents.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.459-466
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• 2007

TCP/IP processing imposes a heavy load on the host CPU when it is processed by the host CPU on a very high-speed network. Recently the TCP/IP Offload Engine (TOE), which processes TCP/IP on a network adapter instead of the host CPU, has become an attractive solution to reduce the load in the host CPU. There have been two approaches to implement TOE. One is the software TOE in which TCP/IP is processed by an embedded processor and the other is the hardware TOE in which TCP/IP is processed by a dedicated ASIC. The software TOE has poor performance and the hardware TOE is neither flexible nor expandable enough to add new features. In this paper we designed and implemented a hybrid TOE architecture, in which TCP/IP is processed by cooperation of hardware and software, based on an FPGA that has two embedded processor cores. The hybrid TOE can have high performance by processing time-critical operations such as making and processing data packets in hardware. The software based on the embedded Linux performs operations that are not time-critical such as connection establishment, flow control and congestions, thus the hybrid TOE can have enough flexibility and expandability. To improve the performance of the hybrid TOE, we developed a hardware-based transmission/reception accelerator that processes important operations such as creating data packets. In the experiments the hybrid TOE shows the minimum latency of about $19{\mu}s$. The CPU utilization of the hybrid TOE is below 6 % and the maximum bandwidth of the hybrid TOE is about 675 Mbps.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.4
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• pp.259-273
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• 2009

Most of large-scale distributed file systems decouple a metadata operation from read and write operations for a file. In the distributed file systems, a certain server named a metadata server (MDS) maintains metadata information in file system such as access information for a file, the position of a file in the repository, the namespace of the file system, and so on. But, the existing systems used restrictive metadata management schemes, because most of the distributed file systems designed to focus on the distributed management and the input/output performance of data rather than the metadata. Therefore, in the existing systems, the metadata throughput and expandability of the metadata server are limited. In this paper, we propose a new non-shared metadata management scheme in order to provide the high metadata throughput and scalability for a cluster of MDSs. First, we derive a dictionary partitioning scheme as a new metadata distribution technique. Then, we present a load balancing technique based on the distribution technique. It is shown through various experiments that our scheme outperforms existing metadata management schemes in terms of scalability and load balancing.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.292-303
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• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.