• Journal of Energy Engineering
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• v.14 no.1
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• pp.46-53
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• 2005

This paper presents a new approach for determining an accurate incentive levels of Direct Load Control (DLC) program using probabilistic techniques. The economic analysis of DLC resources needs to identify the hourly-by-hourly expected energy-not-served resulting from the random outage characteristics of generators as well as to reflect the availability and duration of DLC resources, which results the computational explosion. Therefore, the conventional methods are based on the scenario approaches to reduce the computation time as well as to avoid the complexity of economic studies. In this paper, we have developed a new technique based on the sequential Monte Carlo simulation to evaluate the required expected load control amount in each hour and to decide the incentive level satisfying the economic constraints. In addition, we have applied the variance reduction technique to enhance the efficiency of the simulation. To show the efficiency and effectiveness of the suggested method, the numerical studies have been performed for the modified IEEE 24-bus reliability test system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.459-468
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• 2003

This paper proposes a novel low-cost and high-speed Reed-Solomon (RS) decoder based on a new degree computationless modified Euclid´s (DCME) algorithm. This architecture has quite low hardware complexity compared with conventional modified Euclid´s (ME) architectures, since it can remove completely the degree computation and comparison circuits. The architecture employing a systolic away requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t＋2 basic cells has regularity and scalability since it uses only one processing element. The RS decoder has been synthesized using the 0.25${\mu}{\textrm}{m}$. Faraday CMOS standard cell library and operates at 200MHz and its data rate suppots up to 1.6Gbps. For tile (255, 239, 8) RS code, the gate counts of the DCME architecture and the whole RS decoder excluding FIFO memory are only 21,760 and 42,213, respectively. The proposed RS decoder can reduce the total fate count at least 23% and the total latency at least 10% compared with conventional ME architectures.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.2
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• pp.45-50
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• 2010

An image interpolation is a technique to use for enhancement of image resolution, it have two problems which are image quality degradation of the interpolated result image and high computation complexity. In this paper, to solve the problem, we propose an image interpolation algorithm using loss information estimation and implement the proposed method on portable device. From reduction image of obtained low resolution image, the proposed method can computes error to use image interpolated and estimate loss information by interpolation of the computed error. The estimated loss information is added to interpolated high resolution image with weight factor. We verified that the proposed method has improved FSNR as 2dB than conventional algorithms by experiments. Also, we implemented the proposed method on portable device and checked up real-time action. The proposed algorithm may be helpful for various application for image enlargement and reconstruction.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.49-54
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• 2008

In cryptosystems based on finite fields, a modular multiplication operation is the most crucial part of finite field arithmetic. Also, in multipliers with resource constrained environments, bit-serial output structures are used in general. This paper proposes two efficient bit-serial output multipliers with the polynomial basis representation for irreducible trinomials. The proposed multipliers have lower time complexity compared to previous bit-serial output multipliers. One of two proposed multipliers requires the time delay of $(m+1){\cdot}MUL+(m+1){\cdot}ADD$ which is more efficient than so-called Interleaved Multiplier with the time delay of $m{\cdot}MUL+2m{\cdot}ADD$. Therefore, in elliptic curve cryptosystems and pairing based cryptosystems with small characteristics, the proposed multipliers can result in faster overall computation. For example, if the characteristic of the finite fields used in cryprosystems is small then the proposed multipliers are approximately two times faster than previous ones.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.29-35
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• 2017

This paper presents a high-throughput area-efficient mixed-radix fast Fourier transform (FFT) processor using the efficient scheduling schemes. The proposed FFT processor can support 64, 128, 256, and 512-point FFTs for orthogonal frequency division multiplexing (OFDM) systems, and can achieve a high throughput using mixed-radix algorithm and eight-parallel multipath delay commutator (MDC) architecture. This paper proposes new scheduling schemes to reduce the size of read-only memories (ROMs) and complex constant multipliers without increasing delay elements and computation cycles; thus, reducing the hardware complexity further. The proposed mixed-radix MDC FFT processor is designed and implemented using the Samsung 65nm complementary metal-oxide semiconductor (CMOS) technology. The experimental result shows that the area of the proposed FFT processor is 0.36 mm2. Furthermore, the proposed processor can achieve high throughput rates of up to 2.64 GSample/s at 330 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2C
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• pp.148-155
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• 2006

For the improvement of coding efficiency, the H.264 standard uses new coding tools which are not used in previous coding standards. Among new coding tools, motion estimation using smaller block sizes leads to higher correlation between the motion vectors of neighboring blocks. This characteristic of H.264 is useful for the motion vector recovery. In this paper, we propose the motion vector recovery method based on optical flow. Since the proposed method estimates the optical flow velocity vector from more accurate initial value and optical flow region is limited to 16$\times$16 block size, we can alleviate the complexity of computation of optical flow velocity. Simulation results show that our proposed method gives higher objective and subjective video quality than previous methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.112-121
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• 2002

In this paper, we present a design of a hash processor for data security systems. Two standard hash algorithms, Sha-1(American) and HAS-1600(Korean), are implemented on a single hash engine to support real time processing of the algorithms. The hash processor can also be used as a PRNG(Pseudo-random number generator) by utilizing SHA-1 hash iterations, which is being used in the Intel software library. Because both SHA-1 and HAS-160 have the same step operation, we could reduce hardware complexity by sharing the computation unit. Due to precomputation of message variables and two-stage pipelined structure, the critical path of the processor was shortened and overall performance was increased. We estimate performance of the hash processor about 624 Mbps for SHA-1 and HAS-160, and 195 Mbps for pseudo-random number generation, both at 100 MHz clock, based on Samsung 0.5um CMOS standard cell library. To our knowledge, this gives the best performance for processing the hash algorithms.

• Journal of Communications and Networks
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• v.6 no.3
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• pp.269-279
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• 2004

A new online multi-layer integrated routing (MLIR) scheme that combines IP (electrical) layer routing with WDM (optical) layer routing is investigated. It is a highly efficient and cost-effective routing scheme viable for the next generation integrated optical Internet. A new simplified weighted graph model for the integrated optical Internet consisted of optical routers with multi-granularity optical-electrical hybrid switching capability is firstly proposed. Then, based on the proposed graph model, we develop an online integrated routing scheme called differentiated weighted fair algorithm (DWFA) employing adaptive admission control (routing) strategies with the motivation of service/bandwidth differentiation, which can jointly solve multi-layer routing problem by simply applying the minimal weighted path computation algorithm. The major objective of DWFA is fourfold: 1) Quality of service (QoS) routing for traffic requests with various priorities; 2) blocking fairness for traffic requests with various bandwidth granularities; 3) adaptive routing according to the policy parameters from service provider; 4) lower computational complexity. Simulation results show that DWFA performs better than traditional overlay routing schemes such as optical-first-routing (OFR) and electrical-first-routing (EFR), in terms of traffic blocking ratio, traffic blocking fairness, average traffic logical hop counts, and global network resource utilization. It has been proved that the DWFA is a simple, comprehensive, and practical scheme of integrated routing in optical Internet for service providers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.12
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• pp.1102-1112
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• 2012

We propose a cell selection and resource allocation scheme that assigns users to nearby accessible cells in heterogeneous wireless networks consisting of macrocell, femtocells, and Wi-Fi access points, under overload situation. Given the current power level of all accessible cells nearby users, the proposed scheme finds all possible cell assignment mappings of which user should connect to which cell to maximize the number of users that the network can accommodate at the same time. We formulate the cell selection problem with heterogeneous cells into an optimization problem of binary integer programming, and compute the optimal solution. We evaluate the proposed algorithm in terms of network access failure compared to a local ad-hoc based cell selection scheme used in practical systems using network level simulations. We demonstrate that our cell selection algorithm dramatically reduces network access failure in overload situation by fully leveraging network resources evenly across heterogeneous networks. We also validate the practical feasibility in terms of computational complexity of our binary integer program by measuring the computation time with respect to the number of users.

• KIPS Transactions on Software and Data Engineering
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• v.9 no.2
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• pp.39-44
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• 2020

In this paper, we show a modified Diffie-Hellman key exchange protocol that can exchange keys by exposing only minimal information using pre-computable session key pairs. The discrete logarithm problem, which provides the safety of existing Diffie-Hellman and Diffie-Hellman based techniques, is modified to prevent exposure of primitive root. We prove the algorithm's operation by applying the actual value to the proposed scheme and compare the execution time and safety with the existing algorithm, shown that the security of the algorithm is improved more than the product of the time complexity of the two base algorithms while maintaining the computation amount at the time of key exchange. Based on the proposed algorithm, it is expected to provide a key exchange environment with improved security.