• Journal of Digital Convergence
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• v.7 no.4
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• pp.169-180
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• 2009

IT governance implies a system in which all stakeholders with a given organization, including the board, internal customers, and related areas such as finance provide the necessary input into their decision-making process. However, the concepts of IT governance are broad and ambiguous, so IT governance is eventually needed multi-criteria decision making. This paper presents a hierarchical structure to better understand the relationship between control structure and the complexity of collective behavior with respect to IT governance and proposes a corresponding fuzzy model for analyzing IT governance complexity based on an extensive literature review. The results of this study are expected to provide a clearer understanding of how the concerns of IT governance behave and how they interact and form the collective behavior of the entire system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.887-901
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• 2002

Software management model divided into the software project model and design estimation model, software matrices model, reliability growth model, process improvement model(or process maturity model) etc. Among these software management models, software complexity model make an estimated of the product software. For a practice of software managed, need to guideline of the static analysis of software. Especially, Software complexity model introduced for the estimation of software quantity and program complexity. In case of measurement the software matrices, its need for us to analysis of software quality and products. On the other hand, we known that complexity program include many defects and consuming of source cost. So, we apply to complexity model using of the program complexity, control structure and volume matrices, interface metrics, process complexity metrics method. In this paper, we represent that the analysis of fault data detected during the system test. Also, we analysis of program control structure and interface, volume matrices in various aspect of switching software. Others, their results utilized similar of project and system development.

• ETRI Journal
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• v.25 no.5
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• pp.345-355
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• 2003

In this paper, we propose a method for designing a class of M-channel, causal, stable, perfect reconstruction, infinite impulse response (IIR), and parallel uniform discrete Fourier transform (DFT) filter banks. It is based on a previously proposed structure by Martinez et al. [1] for IIR digital filter design for sampling rate reduction. The proposed filter bank has a modular structure and is therefore very well suited for VLSI implementation. Moreover, the current structure is more efficient in terms of computational complexity than the most general IIR DFT filter bank, and this results in a reduced computational complexity by more than 50% in both the critically sampled and oversampled cases. In the polyphase oversampled DFT filter bank case, we get flexible stop-band attenuation, which is also taken care of in the proposed algorithm.

• Journal of the Society of Naval Architects of Korea
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• v.56 no.1
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• pp.1-10
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• 2019

Naval ship design and related other activities can be characterized by the complexity of the interactions among products, activities, and disciplines. Such complexities often result in inferior designs, cost overrun, and late-delivery. Hence there exist tremendous interests in both improving the design process itself and optimizing the interactions among design activities. This paper looks at the complexity of designing naval ships thereby leading to the innovation of current ship design practices using design structure matrix. It can be used to induce the optimal ordering of design activities as well as identify sources of complexities. The method presented here identifies coupled design activities useful for reducing the complexity of naval ship design as well as optimally reordering design activities. This paper recommends the use of design structure matrix method suitable for numerically optimizing the concept design process of naval ship, and reducing cost and time required in designing naval ships by modeling and analyzing the design activities and engineering tasks, defined in systems engineering planning documents.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.45-48
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• 2005

In this paper, we propose a new fast running FIR filter structure that improves the convergence speed of adaptive signal processing and reduces the computational complexity. The proposed filter is applied to wavelet based adaptive algorithm. Actually we compared the performance of the proposed algorithm with other algorithm using computer simulation of adaptive noise canceler based on synthesis speech. As the result, We know the proposed algorithm is prefer than the existent algorithm.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.355-356
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• 2006

MPEG-4 ER-BSAC decoder employes a full search method for maximum significance search and arithmetic decoding position search in spectral data decoding procedure. Then the search procedure have the most complexity. This paper proposes the new search method, the maximum significance tree structure, for the optimized implementation of BSAC decoder.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.533-534
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• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.385-388
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• 2002

This paper proposes a new GSC (Generalized Sidelobe Canceller) structure, called HLMS-GSC. Compared to Griffiths and Jim's GSC structure, the number of complex multiplication required is reduced to one half. The simulation results show that the minimum mean square errors and performance of nulling jammers by using HLMS-GSC are almost the same compared to Griffiths and Jim's GSC, although the complexity is reduced significantly. As a result, the proposed adaptive beamformer is good for real time implementation, since it has low complexity compared to previous GSC structures.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.389-392
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• 2002

This paper propose a new GSC (Generalized Sidelobe Canceller) structure, called HFLMS-GSC. The number of complex multiplication required is reduced to one half compared to FLMS-GSC. The simulation results show that mean square error converging and jamming signal removing characteristics are almost the same compared to FLMS-GSC, although the complexity is reduced significantly. As a result, the proposed structure is good for real time implementation, since it has low complexity compared to previous GSC structures.

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.325-343
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• 2012

This paper proposes the coding method to predict the split structure of LCU in the current frame on the basis of the reference frame or temporally-previous frame. HEVC encoder determines split structure according to image characteristics in LCU which is an basic element of CU. The split structure of the current LCU is very similar to the split structure of collocated LCU in the reference frame or temporally-previous frame. Thus, this paper proposes the method to reduce the encoder computational complexity by predicting split structure of the current LCU on the basis of that of collocated LCU in the reference frame or temporally-previous frame. And it also proposes the method to reduce the BD-Bitrate by coding after the prediction of the CU split information. The simulation results of changing only encoder showed that the mean of encoder computational complexity was lower by 21.3%, the decoder computational complexity was negligible change and the BD-Bitrate increase by the maximum of 0.6%. Also, the method changing encoder, bitstream, and decoder improves the mean of encoder computational complexity was lower by 22%, the decoder computational complexity was negligible change and the BD-Bitrate is improved to the maximum of 0.3%. When compared with the conventional method, indicating that the proposed method is superior.