• 대한전자공학회논문지SD
• /
• 제40권9호
• /
• pp.714-723
• /
• 2003

아날로그 IC의 signal swing을 증가시키고 노이즈를 감소시키는 효율적이고 기본적인 방법은 fully-differential 회로를 이용하는 것이다. 하지만 differential-mode 신호처리에 영향을 미치는 common-mode 출력 레벨을 안정되도록 하기 위해서는 common-mode feedback (CMFB)회로가 사용되어야 한다. 본 논문에서는 CMFB 구성과 출력 레벨을 안정되도록 하기 위해 사용되는 에러증폭기 회로들의 설계 방법을 기술하고, 트랜지스터들로만 구성된 효율적인 저 증폭도 에러증폭기론 제안한다. 제안된 에러증폭기는 phase margin 증가 및 differential-mode 입력 신호의 swing 폭을 증가시킨다.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2016년도 전력전자학술대회 논문집
• /
• pp.487-488
• /
• 2016

In this paper, a new active circuit for common-mode voltage (CMV) cancellation in three-level NPC (neutral-point clamped) inverters is proposed, which can avoid the saturation of the common-mode transformer (CMT). The proposed circuit utilizes an additional three-level leg to produce the compensating CMV of the NPC inverters, which eliminates the CMV of the inverter through the CMT.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2000년도 전력전자학술대회 논문집
• /
• pp.186-190
• /
• 2000

This paper propose a "Active common-mode voltage damper circuit" that capable of a suppression of a common-mode voltage produced in the PWM VSI. The four level half-bridge PWM inverter circuit and common-mode transformer are incorporated into the "Active common-mode voltage damper" the design method of which is presented Effect of "Active common-mode voltage damper" in this paper verifies a propriety and effectiveness in 2.2[kW] induction motor drive using IGBT inverter. Experimental results show that "common-mode voltage damper" makes contributions to reducing a high frequency leakage current and common-mode voltage.leakage current and common-mode voltage.

• 전력전자학회논문지
• /
• 제5권5호
• /
• pp.443-450
• /
• 2000

PWM 인버터에 의하여 구동되는 유도전동기는 뛰어난 동작특성을 가지고 있지만, 커먼 모드 전압과 고주파 누설전류를 야기한다. 이 고주파 누설 전류는 여러가지 문제점을 일으킨다. 본 논문에서는 이러한 문제점을 일으키는 고주파 누설 전류와 커먼 모드 진압을 감쇄하기 위하여 커먼 모드 전압과 크기가 같고 반대극성을 가진 전압을 4 level half bridge 인버터를 이용하여 생성하고, 이것을 커먼 모드 transformer에 인가하여 고주파 누설 전류 역시 감쇄시킬 수 있는 새로운 형태의 능동형 커먼 모드 전압 감쇄기를 제안한다. 그리고 제안한 감쇄기의 동작 성능을 시뮬레이션과 실험을 통하여 검증하였다.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
• /
• 제55권5호
• /
• pp.265-270
• /
• 2006

In this paper EMI problems with induction motor drive system using multi-level inverters are investigated. The high power multi-level inverter usually operates with low switching frequency and produces large noises. Generally, EMI consists of the conduction component through source lines and emission component emitted to the space. This conduction component can be classified to the common-mode between source line and ground, and the normal-mode between lines. The EMI filters for the induction motor drive system are designed and implemented to reduce EMI noise. Finally the designed system is verified by the experiment. The experimental results show that both the normal mode and common mode noises are greatly reduced compared to the system without filters.

• Journal of Power Electronics
• /
• 제12권4호
• /
• pp.548-558
• /
• 2012

In this paper, a novel offset-based single-state pulse width modulation (PWM) method for achieving zero common-mode voltage (CMV) and reducing switching losses in multilevel inverters is presented. The specific active switching state of the zero common-mode (ZCM) voltage that approximates the reference voltage can be deduced from the switching state sequence of the reduced CMV phase disposition PWM (CMV PD PWM) method. From the reference leg voltages for the zero common-mode voltage, an N-to-2-level transformation defines a virtual two-level inverter and the corresponding nominal leg voltage references. The commutation process of the reduced CMV PD PWM method in a multilevel inverter and its outputs can be simply followed in a nominal switching time diagram for the virtual inverter. The characteristics of the reduced CMV PD PWM and the single-state PWM for zero common-mode voltage are analyzed in detail in this paper. The theoretical analysis of the proposed PWM method is verified by experimental results.

• 전력전자학회논문지
• /
• 제19권6호
• /
• pp.488-493
• /
• 2014

This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
• /
• pp.438-442
• /
• 2001

Much attention has given to EMI effects created by variable speed ac drive system. This paper focuses on the switching technique to mitigate common mode voltage. Zero switching states of inverter control invoke large common mode voltage. Using inversed carrier wave, zero switching states are removed. In addition, proposed technique is easy to apply to existing 2-level inverter design. And common mode mitigation technique for sinusoidal PWM is also presented. Proposed switching technique is implemented with a 2.2kw 1735rpm induction motor.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2001년도 전력전자학술대회 논문집
• /
• pp.434-437
• /
• 2001

Much attention has given to EMI effects created by variable speed ac drive system. This paper focuses on the switching technique to mitigate common mode voltage. Zero switching states of inverter control invoke large common mode voltage. Using inversed carrier wave, zero switching states are removed. In addition, proposed technique is easy to apply to existing 2-level inverter design. Simulation results show that common mode voltages adapting proposed technique are reduced regarding conventional method.

• Journal of Power Electronics
• /
• 제19권1호
• /
• pp.108-118
• /
• 2019

This paper proposes a DC-link voltage balance controller using the fourth-phase of a three-level neutral-point clamped (NPC) PWM converter with medium vector selection (MVS) PWM for common-mode voltage reduction. MVS PWM makes the voltage reference by synthesizing the voltage vectors that cannot generate common-mode voltage. This PWM method is effective for reducing the EMI noise emitted from converter systems. However, the DC-link voltage imbalance problem is caused by the use of limited voltage vectors. Therefore, in this paper, the effect of MVS PWM on the DC-link voltage of a three-level NPC converter is analyzed. Then a proportional-derivative (PD) controller for the DC-link voltage balance is designed from the DC-link modeling. In addition, feedforward compensation of the neutral point current is included in the proposed PD controller. The effectiveness of the proposed controller is verified by experimental results.