• 제목/요약/키워드: Common-mode current(CMC)

검색결과 3건 처리시간 0.016초

EMI Noise Reduction with New Active Zero State PWM for Integrated Dynamic Brake Systems

  • Baik, Jae-Hyuk;Yun, Sang-Won;Kim, Dong-Sik;Kwon, Chun-Ki;Yoo, Ji-Yoon
    • Journal of Power Electronics
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    • 제18권3호
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    • pp.923-930
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    • 2018
  • Based on the application of an integrated dynamic brake (IDB) system that uses a PWM inverter fed-AC motor drive to operate the piston, a new active zero state PWM (AZSPWM) is proposed to improve the stability and reliability of the IDB system by suppressing the conducted electro-magnetic interference (EMI) noise under a wide range of load torque. The new AZSPWM reduces common-mode voltage (CMV) by one-third when compared to that of the conventional space vector PWM (CSVPWM). Although this method slightly increases the output current ripple by reducing the CMV, like the CSVPWM, it can be used within the full range of the load torque. Further, unlike other reduced common-mode voltage (RCMV) PWMs, it does not increase the switching power loss. A theoretical analysis is presented and experiments are performed to demonstrate the effectiveness of this method.

3레벨 4레그 PWM 컨버터의 커먼 모드 전압 저감 (Common-mode Voltage Reduction of Three Level Four Leg PWM Converter)

  • 지승준;고상기;김현식;설승기
    • 전력전자학회논문지
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    • 제19권6호
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    • pp.488-493
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    • 2014
  • This paper presents a carrier-based pulse-width modulation(PWM) method for reducing the common-mode voltage of a three-level four-leg converter. The idea of the proposed PWM method is intuitive and easy to be implemented in digital signal processor-based converter control systems. On the basis of the analysis of space-vector PWM(SVPWM) and sinusoidal PWM(SPWM) switching patterns, the fourth leg pole voltage of the three-phase converter called "f leg pole voltage" is manipulated to reduce the common-mode voltage. To synthesize f leg pole voltage for the suppression of the common-mode voltage, positive and negative pole voltage references of f leg are calculated. An offset voltage is also deduced to prevent the distortion of a, b, and c phase voltages. The feasibility of the proposed PWM method is verified by simulation and experimental results. The common-mode voltage of the proposed PWM method in peak-to-peak value is 33% in comparison with that of the conventional SVPWM method. The transition number of the common-mode voltage is also reduced to 25%.

A New Active Zero State PWM Algorithm for Reducing the Number of Switchings

  • Yun, Sang-Won;Baik, Jae-Hyuk;Kim, Dong-Sik;Yoo, Ji-Yoon
    • Journal of Power Electronics
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    • 제17권1호
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    • pp.88-95
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    • 2017
  • To reduce common-mode voltage (CMV), various reduced CMV pulse width modulation (RCMV-PWM) algorithms have been proposed, including active zero state PWM (AZSPWM) algorithms, remote state PWM (RSPWM) algorithms, and near state PWM (NSPWM) algorithms. Among these algorithms, AZSPWM algorithms can reduce CMV, but they increase the number of switchings compared to the conventional space vector PWM (CSVPWM). This paper presents a new AZSPWM algorithm for reductions in both the CMV and total number of switchings in BLAC motor drives. Since the proposed AZSPWM algorithm uses only active voltage vectors for motor control, it reduces CMV by 1/3 compared to CSVPWM. The proposed AZSPWM algorithm also reduces the total number of switchings compared to existing AZSPWM algorithms by eliminating the switchings required from one sector to the next. The performance of the proposed algorithm is verified by analyses, simulations, and experimental results.